Staggered Sub-Block Read Operations for Memory Peak Current Reduction
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Solution Overview
Problem
As memory devices evolve with increased word line layers, they face challenges with higher word line memory hole capacitance and peak supply current Icc associated with the supply voltage Vcc, leading to undesirable current spikes.
Innovation Solution
Implementing a method where memory blocks are divided into sub-blocks, with each sub-block accessed at a different time, incorporating a time delay and word line voltage ramp rate control to stagger read operations, reducing peak supply current Icc by adjusting the time of read operations and ramp rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word line layers is increased to increase memory storage capacity, then the memory storage capacity is improved, but the peak current Icc associated with the supply voltage Vcc increases
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block) that can be accessed independently at different times. This segmentation allows the read operations to be staggered, preventing simultaneous activation of all word lines and thereby reducing the peak current Icc while maintaining the total memory capacity
Solution Approach 2:
The patent implements periodic action by introducing a time delay between reading the first sub-block and reading the second sub-block. This time-delayed periodic access pattern ensures that word lines are activated in sequence rather than simultaneously, reducing the peak current demand while maintaining continuous memory operation
2Quantity of substance
If the number of word line layers is increased, then the memory storage capacity is improved, but the word line memory hole capacitance increases
Solution Approach 1:
By segmenting the memory block into sub-blocks with separate row decoders, the patent reduces the capacitance burden on any single word line. Each sub-block handles a portion of the total word lines, distributing the capacitive load and reducing the energy required for voltage transitions on individual word lines while maintaining overall high storage capacity
Data Source
AI summary
A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.