Nonvolatile Memory Page Buffer Parallel Verification
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Solution Overview
Problem
High-capacity nonvolatile memory devices face increased failure rates during manufacturing due to the complexity of storing multiple bits in a single memory cell, which complicates program verify operations and reduces storage efficiency.
Innovation Solution
A nonvolatile memory device with a page buffer system that includes two page buffers connected to different memory cells, allowing for the storage and processing of sensing data to detect errors through binary logic operations, thereby determining program errors and reducing the time required for program verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in a single memory cell increases to achieve high capacity, then storage capacity increases in multiple, but the failure rate during manufacturing process increases
Solution Approach 1:
The patent segments the verification process by introducing multiple page buffers (first page buffer and second page buffer) to handle sensing data from different memory cells independently. This segmentation allows parallel processing of verification operations, reducing the overall time and complexity while maintaining high storage capacity through multi-bit memory cells.
2Loss of time
If multiple page buffers are introduced to process sensing data from different memory cells, then program verify time is reduced through parallel processing, but device complexity increases
Solution Approach 1:
The patent merges the verification operations of multiple memory cells by having the second page buffer receive and accumulate sensing data from both the first and second memory cells. This merging approach consolidates the verification process, reducing overall verification time while managing device complexity through systematic data accumulation and comparison operations.
3Measurement precision
If sensing data from multiple memory cells is accumulated and processed, then error detection accuracy improves, but processing complexity increases
Solution Approach 1:
The patent introduces an intermediary accumulation process where the second page buffer receives sensing data from multiple memory cells and accumulates it before final verification. This intermediary step organizes the data flow systematically, improving error detection accuracy by comparing accumulated data against expected values while managing processing complexity through structured intermediate storage and comparison operations.
Data Source
AI summary
A nonvolatile memory device may include a cell array, a first page buffer, and a second page buffer. The first page buffer may be connected to a first memory cell of the cell array and may store first sensing data generated by sensing whether a program operation of the first memory cell is completed during a program verify operation. The second page buffer may be connected to a second memory cell of the cell array. During the program verify operation, the second page buffer may generate and store first verify data based on second sensing data generated by sensing whether a program operation of the second memory cell is completed, may receive the first sensing data from the first page buffer, and may store second verify data generated by accumulating the first sensing data and the first verify data.