Semiconductor Memory Repair Fuse Integration
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Solution Overview
Problem
As semiconductor memory devices increase in capacity and integration, the circuit area required for repair operations expands, and the reliability of repair information storage becomes a concern due to the inefficiencies in conventional redundancy and fuse-based systems, leading to increased waste from failed memory cells.
Innovation Solution
A semiconductor memory device design that includes a memory array region with normal and redundancy cells, a repair fuse block for programming repair addresses, a fuse information storage block with a memory cell structure for storing and refreshing repair information, and a repair control block for activating redundant paths, minimizing circuit area and ensuring reliable repair operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy memory cells and repair fuse circuits are added to replace failed memory cells, then the reliability of the semiconductor memory device is improved, but the circuit area occupied by the device increases
Solution Approach 1:
The patent merges the repair fuse circuit and fuse information storage circuit into a single integrated block. The fuse information storage circuit is configured to directly store repair information from the repair fuse circuit, eliminating the need for separate storage circuits. This integration reduces the overall circuit area while maintaining the reliability function of replacing failed memory cells through repair operations.
Solution Approach 2:
The fuse information storage circuit is designed to serve multiple functions: storing repair information from the repair fuse circuit, providing this information to the repair control circuit, and being refreshed simultaneously with normal and redundancy memory cells. This multi-functionality reduces the need for additional dedicated circuits, thereby reducing overall circuit area while ensuring reliable repair operations.
2Quantity of substance
If the capacity of the semiconductor memory device is increased, then the storage capability is improved, but the number of required repair fuse circuits and fuse information storage circuits increases, leading to greater circuit area occupation
Solution Approach 1:
The patent integrates the repair fuse circuit and fuse information storage circuit into a unified structure. As memory capacity increases, the integrated block scales more efficiently than separate circuits would require, reducing the proportional circuit area dedicated to repair operations while maintaining the necessary repair functionality for the larger memory array.
Solution Approach 2:
The repair system is segmented into functional blocks within the integrated structure: the repair fuse circuit for storing repair addresses, the fuse information storage circuit for holding this information, and the repair control circuit for executing repairs. This segmentation allows each component to be optimized for its specific function while the overall integration reduces total area occupation as capacity scales.
3Reliability
If a dice cell structure is adopted to ensure reliability of the unit fuse set latch, then the reliability of repair information storage is improved, but the circuit area occupied by the unit fuse set latch increases
Solution Approach 1:
The unit fuse set latch is merged with the fuse information storage circuit, allowing the latch to share circuit resources with the storage function. This integration reduces the area occupied by the latch while maintaining its reliability through the combined structure that leverages the storage circuit's inherent reliability features.
Solution Approach 2:
The unit fuse set latch is designed to serve multiple purposes: ensuring reliable storage of repair information and simultaneously functioning as part of the integrated fuse information storage circuit. This multi-functionality allows the latch to maintain high reliability while occupying less area than a dedicated standalone latch would require.
Data Source
AI summary
A semiconductor memory device includes a memory array region including normal cells and redundancy cells; a repair fuse block including a plurality of fuse sets suitable for programming repair addresses of the repair target cells as repair information, the repair fuse block being suitable for outputting the programmed repair information, in response to a boot-up signal; a fuse information storage block including a plurality of memory cells for storing the repair information outputted from the repair fuse block, the plurality of memory cells being refreshed simultaneously with the normal cells and the redundancy cells of the memory array region; and a repair control block suitable for comparing the repair information stored in the fuse information storage block and an address to generate a repair control signal to selectively activate redundant paths between the repair target cells and the redundancy cells.