3D Semiconductor Memory Block Segmentation for Erase Reliability
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, the reliability of erase operations is compromised, and power consumption is unnecessary due to shared bit lines and source lines among memory blocks, leading to inefficiencies in data storage.
Innovation Solution
The semiconductor system is designed with memory blocks arranged in both longitudinal and vertical directions, where sub-memory blocks share bit lines but not word lines and source lines, allowing for controlled voltage differences to improve erase operation reliability and reduce power consumption by separately erasing selected memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sub-memory blocks share bit lines and source lines to reduce device complexity, then device complexity is reduced, but erase operation reliability deteriorates and power consumption increases
Solution Approach 1:
The patent divides memory blocks into multiple sub-memory blocks (first sub-memory blocks and second sub-memory blocks) that share bit lines and source lines. During erase operations, the system selectively applies different voltages to different sub-memory blocks, segmenting the erase operation to ensure reliable erasure of selected blocks while maintaining shared line architecture for complexity reduction.
Solution Approach 2:
The patent applies different voltage conditions to different sub-memory blocks sharing the same bit lines and source lines. By controlling word line voltages locally for each sub-memory block, the system achieves reliable erase operations in selected blocks while maintaining the shared line structure, thus resolving the contradiction between device complexity and erase reliability.
2Device complexity
If sub-memory blocks share bit lines and source lines to reduce device complexity, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent segments the memory block into first and second sub-memory blocks that share bit lines and source lines. During erase operations, the system selectively activates only the required sub-memory blocks by applying appropriate voltages to their word lines, reducing unnecessary power consumption while maintaining the space-efficient shared line architecture.
Solution Approach 2:
The patent implements partial action by applying erase voltages only to the specific sub-memory blocks that require erasure, rather than activating all sub-memory blocks connected to the shared bit lines and source lines. This selective activation reduces power consumption while maintaining the benefits of the shared line structure.
3Reliability
If voltage difference is increased to erase memory cells, then erase operation reliability is improved, but power consumption increases
Solution Approach 1:
The patent divides the memory into sub-memory blocks and applies high voltage differences only to the specific sub-memory blocks requiring erasure. By segmenting the voltage application to only the necessary blocks rather than the entire memory array, the system achieves reliable erasure while minimizing overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of erase operations and minimizes power consumption by applying distinct voltages to different word and source line groups within the memory blocks, optimizing data storage efficiency.
Implementation Method 1
increasing a voltage difference between a channel and memory cells of the first sub-memory block of a selected memory block to erase the memory cells included in the first sub-memory block
Data Source
AI summary
A semiconductor system includes a data storage unit including memory blocks, a circuit group and a control circuit, wherein the memory blocks store data therein and are arranged in a longitudinal direction and a vertical direction. The circuit group is suitable for performing a program, read or erase operation on the memory blocks, and the control circuit controls the circuit group. A memory control unit is suitable for controlling the data storage unit, wherein each of the memory blocks includes a plurality of sub-memory blocks. The sub-memory blocks arranged in the longitudinal direction share bit lines and do not share word lines and source lines. Further, the sub-memory arranged in the vertical direction share the bit lines or the source lines.