Flash Memory Programming Order to Reduce Disturbance
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Solution Overview
Problem
In flash memory devices, the nearest memory cell to the bit line often experiences the worst electrical characteristics due to the program disturbance phenomenon, affecting data storage and retrieval efficiency.
Innovation Solution
A semiconductor device with a memory string comprising a drain selection transistor, memory cells, and a source selection transistor, configured to operate in response to specific voltages, and an operation circuit that performs sequential programming operations on memory cells to improve electrical characteristics and reduce program disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are programmed in a single sequence, then programming speed is improved, but program disturbance phenomenon worsens causing worst electrical characteristics in cells nearest to bit line
Solution Approach 1:
The patent divides the memory cell programming into three separate operations: first operation for cells adjacent to drain selection transistor, second operation for cells adjacent to source selection transistor, and third operation for remaining cells. This segmentation allows different programming sequences to be applied to different cell groups, resolving the contradiction by maintaining high overall programming speed while preventing program disturbance in specific vulnerable cells through targeted programming sequences.
Solution Approach 2:
The patent applies preliminary actions by programming cells adjacent to the drain selection transistor first (in the first operation), before programming other cells. This preliminary programming of vulnerable cells prevents program disturbance from subsequent operations, as these cells are already programmed and less susceptible to disturbance from later programming activities on other cells.
2Productivity
If program voltage is applied to all word lines simultaneously, then programming efficiency is improved, but program disturbance to unselected cells increases
Solution Approach 1:
The patent segments the programming process into three distinct operations that apply program voltage to different sets of word lines in sequence. The first operation targets word lines adjacent to the drain selection transistor, the second operation targets word lines adjacent to the source selection transistor, and the third operation targets remaining word lines. This segmentation ensures that at any given time, program voltage is applied only to a subset of word lines, reducing program disturbance to unselected cells while maintaining overall programming efficiency through the structured sequence.
Data Source
AI summary
A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a drain selection line, word lines and a source selection line. The semiconductor device may include an operation circuit configured for performing a program operation. The operation circuit may be configured for sequentially performing a first operation, a second operation, and a third operation. In the first operation memory cells adjacent to the drain selection transistor may be programmed. In the second operation memory cells adjacent to the source selection transistor may be programmed. In the third operation remaining memory cells may be programmed.