Semiconductor Memory Page Buffer Dual Sensing Latch Verification
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in programming speed due to the need for multiple verification operations, which increase the time required for storing data, especially when programming multiple bits per memory cell.
Innovation Solution
The semiconductor memory device incorporates a page buffer with first and second switching devices and sensing latch units, controlled by a control logic that transfers sensing signals to reflect threshold voltages on a sensing node, allowing for simultaneous sensing and data transfer during verification operations, effectively reducing the number of verification steps needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verification operations are performed sequentially to ensure data accuracy, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent combines two verification operations into a single unified operation by using a dual sensing latch structure (first and second sensing latch units) that simultaneously verify two different data values against the memory cell threshold voltage. The control logic coordinates both verifications in parallel, merging what would traditionally be sequential operations into one concurrent process, thereby reducing total verification time while maintaining accuracy.
Solution Approach 2:
The patent transitions from sequential verification (one-dimensional time progression) to parallel verification by introducing an additional operational dimension. The first and second sensing latch units operate simultaneously on different data values, effectively adding a spatial/parallel dimension to the verification process, which reduces the time required without sacrificing verification thoroughness.
2Manufacturing precision
If multiple verification operations are performed to narrow threshold voltage distribution, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent merges multiple verification functions into a single parallel operation using the dual sensing latch units. Both latch units simultaneously evaluate different data values against the memory cell threshold, achieving the same threshold voltage distribution narrowing effect that would require multiple sequential operations, thereby improving productivity while maintaining manufacturing precision.
Solution Approach 2:
The patent enables continuous useful action by keeping both sensing latch units actively engaged in verification simultaneously. Rather than pausing between verification steps, the system maintains continuous verification activity across multiple data values in parallel, ensuring that the threshold voltage distribution is narrowed efficiently without idle time, thus improving productivity.
3Device complexity
If sequential verification operations are used, then device complexity is reduced, but loss of time increases
Solution Approach 1:
The patent combines multiple verification operations into a single coordinated process using the control logic that manages both sensing latch units simultaneously. While the control logic becomes slightly more complex to coordinate parallel operations, this increase is offset by the elimination of sequential timing delays, achieving net time reduction with manageable complexity.
Solution Approach 2:
The patent introduces parallelism as an additional operational dimension, allowing verification of multiple data values to proceed simultaneously rather than sequentially. This dimensional change from linear to parallel processing reduces verification time while the control logic manages the increased complexity through coordinated signal control of both sensing latch units.
Data Source
AI summary
A semiconductor memory device includes a memory cell, a page buffer including a first and a second switching devices coupled in common to a sensing node coupled to the memory cell through a bit line and a first and a second sensing latch units coupled to the sensing node, respectively, through the first and the second switching devices, and a control logic suitable for transferring a first and a second sensing signals, respectively, to the first and the second switching devices when a threshold voltage of the memory cell is reflected on the sensing node through the bit line during a verification operation. The first and the second switching devices are turned on or off, respectively, in response to the first and the second sensing signals, and data are sensed by the first and the second sensing latch units.