SSD Memory Controller Segmentation for Concurrent Access
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Solution Overview
Problem
Current SSDs are limited by sequential transfer rates and random access latencies, particularly in mixed read-write workloads, due to host transfer rate limitations and initial access latencies of NAND flash memory, which restrict overall system performance.
Innovation Solution
A nonvolatile storage device design featuring multiple independent memory control units connected via a crossbar switch to a host system interface and abstraction layer, allowing concurrent read and write accesses to nonvolatile memory devices, thereby enhancing performance by distributing data loads and reducing write amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single memory controller is used to access NAND flash memory, then device complexity is reduced, but productivity is limited due to sequential access constraints and host transfer rate limitations
Solution Approach 1:
The patent divides the memory controller into multiple independent control units (first control unit, second control unit, etc.), each capable of independently accessing different banks of NAND flash memory. This segmentation allows parallel read and write operations to occur simultaneously across different memory banks, thereby increasing overall data transfer rates without requiring a single complex controller to handle all operations sequentially.
Solution Approach 2:
The patent introduces a crossbar switch architecture that adds a dimensional layer of parallelism between multiple control units and multiple memory banks. This crossbar configuration enables multiple control units to simultaneously access multiple different banks, creating a two-dimensional parallel access pattern that significantly enhances productivity beyond what a single controller could achieve.
2Adaptability or versatility
If random access operations are performed on NAND flash memory, then data flexibility is improved, but initial access latency increases significantly
Solution Approach 1:
The patent segments memory into multiple independent banks, each accessible by dedicated control units. This segmentation allows random access operations to be distributed across multiple banks simultaneously, reducing the latency impact on any single access operation while maintaining the flexibility to perform random reads and writes as needed.
Solution Approach 2:
The patent implements a cache memory that stores frequently accessed data blocks before they are written to or read from NAND flash memory. This preliminary action in the cache reduces the latency of random access operations by serving data from faster memory, thereby maintaining adaptability for random access patterns while reducing the time penalty associated with NAND flash's inherent latency.
3Loss of substance
If write combining is implemented to reduce write amplification, then loss of substance is reduced, but device complexity increases due to additional control logic
Solution Approach 1:
The patent assigns different control units to handle read operations and write operations separately. This segmentation allows write combining logic to be distributed across multiple control units rather than concentrated in a single controller, reducing the complexity burden on any single unit while collectively achieving effective write combining across the entire memory system.
Solution Approach 2:
The patent merges the capabilities of multiple control units to collectively perform write combining operations. By coordinating writes across multiple banks through the crossbar switch architecture, the system achieves reduced write amplification through combined write operations while distributing the control logic complexity across multiple simpler control units rather than requiring one highly complex controller.
Data Source
AI summary
A nonvolatile storage device adapted for use with computers, workstations and other processing apparatuses. The storage device includes a printed circuit board, a nonvolatile memory array comprising at least two sub-arrays that contain nonvolatile solid-state memory devices, and control circuitry for interfacing with the processing apparatus. The control circuitry includes an abstraction layer and at least two memory control units configured to communicate data, address and control signals with the sub-arrays of the memory devices. A bus connects each memory control unit to a corresponding one of the sub-arrays. The control circuitry further includes a crossbar switch that functionally connects each memory control unit to the abstraction layer. The storage device is capable of overcoming limitations of current SSD designs by enabling independent read and write transfers (accesses) to the memory devices of the storage device, including concurrent read and write accesses.