Autonomous NAND Refresh via Background Scheduler
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Solution Overview
Problem
NAND memories experience data retention loss due to temperature-dependent charge discharge, which exceeds the capability of conventional Error Correction Codes (ECC) algorithms, leading to potential catastrophic system failures, especially at elevated temperatures.
Innovation Solution
A background scheduler is implemented to autonomously refresh and rewrite data in NAND memories at predetermined intervals, locking blocks during operations to prevent data corruption, and adjusting frequencies based on temperature to avoid irreversible data loss, using lower-level communications to interact directly with the memory controller and manage ECC information independently of the file system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC algorithms are used for error correction, then a small number of bit-flips can be detected and corrected, but data retention loss beyond ECC capability occurs at high temperatures leading to catastrophic system failure
Solution Approach 1:
The system performs preliminary actions by periodically rewriting data to alternate blocks before data loss occurs. The background scheduler proactively refreshes data in NAND memories at predetermined intervals, preventing data retention loss before it exceeds ECC correction capability. This preliminary refresh action addresses the root cause of data loss rather than merely correcting errors after they occur.
2Reliability
If software ECC algorithms are implemented to correct higher number of bit-flips, then more errors can be corrected, but CPU availability is affected due to calculation overhead on every NAND access
Solution Approach 1:
Instead of performing complex ECC calculations on every NAND access, the system implements periodic action by scheduling background refresh operations at predetermined intervals. The background scheduler periodically rewrites data to alternate blocks without requiring complex real-time ECC calculations during normal CPU operations, thus maintaining high CPU availability while preventing data retention loss.
Solution Approach 2:
The system creates a copy of data by rewriting it to alternate blocks. Instead of relying on complex ECC algorithms to correct errors in place, the invention copies data to a different physical location (alternate block) where it can be refreshed, effectively creating a redundant copy that prevents data loss without requiring complex real-time error correction calculations.
3Reliability
If frequent rewrite operations are performed to prevent data loss, then data retention is improved, but system contention increases and CPU availability decreases
Solution Approach 1:
The system implements self-service by using idle CPU cycles and background processing to perform rewrite operations. The background scheduler autonomously manages data refresh operations without requiring frequent CPU intervention or blocking system operations. This allows the system to service its own data retention needs during idle periods, minimizing system contention while maintaining reliable data retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents data loss by ensuring reliable data retention across varying temperatures, minimizing system contention, and maintaining CPU availability by scheduling rewrites without requiring frequent erase operations, thus extending the data retention time and preventing corruption.
Implementation Method 1
discharge rate is temperature-dependent as it is a physical phenomenon governed by the Arrhenius equation given by: where AF=Acceleration factor, Ea=Activation energy (0.6 eV for data retention), k=Boltzmann's constant (8.623×10−5 eV/K), T1=Application junction temperature in Kelvin, and T2=Accelerated stress junction temperature in Kelvin
Implementation Method 2
Data bits in NAND memories are stored as charges injected to the floating gate cells of MOSFETs... discharge rate is temperature-dependent... Values for the Arrhenius acceleration factor show that likely to happen in less than one year if an appliance is exposed to an environment such that the temperature of the silicon die of the memory (junction temperature in the equation) reaches about 60° C.
Data Source
AI summary
A background scheduler is provided that utilizes low-level communications (e.g., communications with a generic or controller-specific solid state, non-volatile memory driver) to control locking, reading, rewriting and unlocking of pages of data in the non-volatile memory. Such low-level communications cause data to be rewritten to the non-volatile memory independent of the file system in an effort to avoid data loss prior to an estimated data retention period.