Semiconductor Memory Device Erase Control with Bad String Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in erase operations due to unnecessary verify operations, particularly in multi-plane operations, which slow down the overall processing speed.
Innovation Solution
The implementation of a semiconductor memory device with registers to track the status of each string unit, allowing for the skipping of verify operations for bad strings and optimizing the erase process by selecting only necessary string units for verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verify operations are performed on all string units during erase operations, then reliability of data erasure is improved, but processing speed deteriorates due to unnecessary verify operations on bad strings
Solution Approach 1:
The patent applies preliminary action by performing verify operations only on string units that are likely to require verification, rather than all string units. The control circuit identifies candidate string units based on erase operation patterns and selectively performs verify operations on those candidates, eliminating unnecessary verify operations on bad strings that don't require verification.
2Productivity
If verify operations are skipped for bad strings, then processing speed is improved, but reliability of data erasure deteriorates
Solution Approach 1:
The patent implements feedback by using information from erase operation patterns and previous verify results to dynamically determine which string units require verification. The control circuit continuously monitors erase operation status and adjusts verify operation selection based on feedback from the memory device's actual state, ensuring that necessary verifications are performed while skipping unnecessary ones.
3Measurement precision
If all string units are selected for verify operations, then measurement precision of erase completion is improved, but loss of time increases due to processing all string units including bad strings
Solution Approach 1:
The patent applies the taking out principle by extracting and isolating only the candidate string units that require verification from the complete set of string units. The control circuit identifies and separates candidate string units based on erase operation patterns, then performs verify operations exclusively on this extracted subset, eliminating time consumption from processing all string units including bad strings that don't require verification.
Data Source
AI summary
A semiconductor memory device includes a block including a plurality of string units, each including a plurality of memory cells electrically connected in series, a bad string register in which information indicating which of the string units is a bad string is stored, and a control circuit. The control circuit controls an erase operation on the memory cells, the erase operation including a first erase operation followed by a first verify operation and as needed a subsequent erase operation followed by a subsequent verify operation. During the erase operation, the control circuit skips a verify operation for a string unit if the information in the bad string register indicates the string unit is a bad string.