Bit Line Current Trip Point Modulation for Nonvolatile Memory
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Solution Overview
Problem
As semiconductor memory devices shrink in size, the increasing bit line resistance affects the verify process in non-volatile storage elements, leading to inaccuracies in programming and reading due to variations in bit line resistance based on the distance from the sensing circuit.
Innovation Solution
The system dynamically adjusts the testing of memory cell current by changing the test time or voltage, and uses a charge storage device to account for bit line resistance variations, ensuring accurate programming and reading by maintaining constant charge storage across the sensing circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bit line resistance increases due to device scaling, then the manufacturing density is improved, but the measurement precision of current testing deteriorates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the test time and voltage levels based on the memory cell's position along the bit line. Cells farther from the sensing circuit are tested with longer times and higher voltages to compensate for increased bit line resistance, ensuring consistent measurement precision across all cells despite device scaling.
Solution Approach 2:
The patent implements dynamics by making the test parameters (time and voltage) variable rather than fixed. The testing duration and voltage level are dynamically adjusted according to the cell's distance from the sensing circuit, allowing the system to adapt to varying bit line resistance conditions and maintain accurate current measurement.
2Adaptability or versatility
If the bit line resistance varies with distance from sensing circuit, then the device layout flexibility is improved, but the manufacturing precision of programming and reading deteriorates
Solution Approach 1:
The patent applies local quality by tailoring test parameters to the specific location of each memory cell along the bit line. Cells at different positions receive different test conditions (time and voltage) optimized for their local resistance characteristics, ensuring uniform programming and reading accuracy across the entire array despite layout variations.
Solution Approach 2:
The patent implements feedback by using the measured current information to determine the memory cell state and by adjusting test parameters based on position feedback. The system continuously monitors current flow and uses this feedback to verify programming levels and read data accurately, compensating for bit line resistance variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures accurate and reliable programming and reading of memory cells by compensating for bit line resistance variations, maintaining the integrity of data storage across different positions relative to the sensing circuit.
Implementation Method 1
uses a charge storage device to account for bit line resistance variations, ensuring accurate programming and reading by maintaining constant charge storage across the sensing circuit
Data Source
AI summary
Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.