SIP Semiconductor Test Control Unit Segmentation

Solution Overview

Problem

System in Package (SIP) semiconductor systems face challenges in performing probe tests and repairs due to the lack of direct access to memory devices from outside the package, leading to increased area and cost requirements for internal logic circuits and redundancy analysis configurations.

Innovation Solution

Incorporating a test control unit with IEEE 1149.1 standard interface, electrical fuses for restoring defective storage elements, and input/output terminals for direct communication with external devices, allowing for efficient testing and repair of memory devices within the SIP semiconductor system without relying on external controllers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all input/output terminals are connected to the controller in the package, then noise and operation stability are improved, but probe test and repair operation capability deteriorates

Engineering Contradiction:

Improveoperation stabilityVSAvoidprobe test capability

Core Design Contradiction:

ReliabilityVSEase of repair

Solution Approach 1:

The patent segments the input/output terminals into two functional groups: general I/O terminals connected to the controller for normal operation, and dedicated test terminals connected directly to the memory device for testing and repair operations. This segmentation allows simultaneous achievement of noise reduction (through controller-mediated general I/O) and test capability (through direct test terminal access).

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a test control unit as an intermediary component that manages the dual functionality of the I/O terminals. This unit coordinates between the controller and memory device, enabling test operations to occur independently while maintaining the controller's role in normal operations, thus preserving both stability and testability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of repair

If redundancy analysis configuration is implemented as internal logic circuit, then repair operation capability is improved, but area and cost increase

Engineering Contradiction:

Improverepair operation capabilityVSAvoidpackage area

Core Design Contradiction:

Ease of repairVSArea of stationary object

Solution Approach 1:

The patent introduces a test control unit as an intermediary component that manages the dual functionality of the I/O terminals. This unit coordinates between the controller and memory device, enabling test operations to occur independently while maintaining the controller's role in normal operations, thus preserving both stability and testability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the redundancy analysis functionality from internal logic circuits and implements it through external test terminals and control units. This extraction eliminates the need for additional internal circuitry, reducing package area while maintaining full repair capability through external testing infrastructure.

Inventive Principle:

Principle #2Taking out (Extraction)

3Ease of repair

If redundancy analysis configuration is implemented as internal logic circuit, then repair operation capability is improved, but cost increases

Engineering Contradiction:

Improverepair operation capabilityVSAvoidmanufacturing cost

Core Design Contradiction:

Ease of repairVSEase of manufacture

Solution Approach 1:

The patent extracts the redundancy analysis functionality from internal logic circuits and implements it through external test terminals and control units. This extraction eliminates the need for additional internal circuitry, reducing package area while maintaining full repair capability through external testing infrastructure.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The test control unit and I/O terminals are designed with multi-functionality, serving both normal operational communication and test/repair functions. This universality eliminates the need for separate dedicated repair circuits, reducing overall system complexity and manufacturing cost while maintaining comprehensive repair capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8811101B2SIP semiconductor system

Publication Date: 2014.08.19 SK HYNIX INC

AI summary

A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system.