NAND Flash Word-Line Voltage Control for Read Reliability

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Solution Overview

Problem

Current NAND flash memory devices face challenges in improving the reliability of read operations due to voltage inconsistencies between adjacent word-lines and read word-lines, leading to increased error rates.

Innovation Solution

A method and memory device that adjust the voltage applied to adjacent word-lines based on difference information determined by the distance between the read word-line and the boundary word-line, allowing for controlled voltages to be applied to both the read word-line and adjacent word-line, thereby optimizing read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a uniform voltage is applied to all word-lines during read operations, then the circuit design is simple, but the read reliability deteriorates due to voltage inconsistencies between adjacent word-lines and read word-lines

Engineering Contradiction:
Improveread operation reliabilityVSAvoidvoltage control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different voltage levels to different word-lines based on their specific position and function. The read word-line receives a first voltage level, while adjacent word-lines receive a second voltage level, and non-adjacent word-lines receive a third voltage level. This local differentiation of voltage quality improves read reliability by accounting for the specific electrical characteristics of each word-line's position in the memory array.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the word-line voltage control into distinct groups: the read word-line, adjacent word-lines, and non-adjacent word-lines. Each segment receives a specifically tailored voltage level optimized for its function. This segmentation allows the system to address voltage inconsistencies locally without requiring complex control for the entire word-line array.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the voltage applied to adjacent word-lines is reduced to improve read reliability, then the error rate decreases, but the voltage control mechanism becomes more complex

Engineering Contradiction:
Improveread operation reliabilityVSAvoidvoltage control ease
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent applies voltage reduction selectively only to adjacent word-lines that are immediately next to the read word-line, rather than uniformly reducing voltage across all word-lines. This partial action approach improves read reliability by addressing the specific source of interference (adjacent word-line voltage inconsistencies) without requiring complex voltage control mechanisms for the entire word-line array.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If distinct voltages are applied to word-lines in program and erase regions, then the error rate is reduced, but the voltage generator complexity increases

Engineering Contradiction:
Improveread operation reliabilityVSAvoidvoltage generator complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements local quality by assigning different voltage levels to word-lines based on their operational state (program vs. erase region). Word-lines in the program region receive a first voltage level, while word-lines in the erase region receive a second voltage level. This localized voltage differentiation reduces errors caused by voltage inconsistencies between programmed and erased cells without requiring a completely complex voltage generation system.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9741440B2Memory device and read method of memory device
Publication Date: 2017.08.22 SAMSUNG ELECTRONICS CO LTD
  • US9741440B2 patent drawing
  • US9741440B2 patent drawing
  • US9741440B2 patent drawing

AI summary

In a method of reading a memory device, difference information is generated based on a distance difference between a position of a read word-line and a position of a boundary word-line. The read word-line corresponds to a read address. The boundary word-line corresponds to a last programmed word-line in a memory block included in a memory cell array. A read word-line voltage and an adjacent word-line voltage are determined based on the difference information. The read word-line voltage is applied to the read word-line. The adjacent word-line voltage is applied to an adjacent word-line that is adjacent to the read word-line. A read data corresponding to the read address is outputted based on the read word-line voltage and the adjacent word-line voltage. The read method of the memory device according to example embodiments may be capable of increasing the performance by controlling the voltages applied to the adjacent word-line and the read word-line according to the difference information determined based on the read word-line and the boundary word-line.