EEPROM Array Read Current Reduction via Data Inversion

Solution Overview

Problem

Existing EEPROM memory array structures experience high read current and power consumption when all memory cells are erased, which is unfavorable for low power consumption applications and can affect memory device speed.

Innovation Solution

Incorporating a programming indication bit before each subsidiary memory array and an inversion indication bit after the data unit, with specific rules for setting these bits during programming to reduce the number of '1' bits, thereby minimizing read current by inverting data when necessary.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If all memory cells are erased (set to 1), then the memory array structure can store maximum value, but the read current reaches maximum value causing high power consumption

Engineering Contradiction:

Improvestorage capacityVSAvoidread power consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent inverts the conventional approach by introducing inversion indication bits that allow the memory system to store data in an inverted state. When the inversion indication bit is set, the memory cell stores the inverse of the actual data, which reduces the number of '1' bits in the memory array and consequently reduces the read current and power consumption while maintaining the same storage capacity.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the parameter of data representation by introducing inversion indication bits that modify how data is stored and read. This parameter change allows the system to dynamically adjust the number of '1' bits in the memory array, thereby controlling the read current and power consumption while maintaining full storage capacity.

Inventive Principle:

Principle #35Parameter changes

2Quantity of substance

If all memory cells are erased (set to 1), then the memory array structure can store maximum value, but the read current reaches maximum value affecting memory device speed

Engineering Contradiction:

Improvestorage capacityVSAvoidmemory device speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The patent inverts the conventional approach by introducing inversion indication bits that allow the memory system to store data in an inverted state. When the inversion indication bit is set, the memory cell stores the inverse of the actual data, which reduces the number of '1' bits in the memory array and consequently reduces the read current and power consumption while maintaining the same storage capacity.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the parameter of data representation by introducing inversion indication bits that modify how data is stored and read. This parameter change allows the system to dynamically adjust the number of '1' bits in the memory array, thereby controlling the read current and power consumption while maintaining full storage capacity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9153322B2Memory array device and method for reducing read current of the same

Publication Date: 2015.10.06 SHANGHAI HUAHONG GRACE SEMICON MFG CORP

AI summary

A memory array device is disclosed, which includes a plurality of memory array rows, each memory array row including a plurality of subsidiary memory arrays and a switch arranged between every adjacent two subsidiary memory arrays; wherein each subsidiary memory array includes: a memory unit for storing a data; a programming indication bit arranged prior to the memory unit for indicating whether the subsidiary memory array has been programmed; and an inversion indication bit arranged subsequent to the memory unit for indicating whether a data had been inverted before being written in the memory unit of the subsidiary memory array. A method for reducing a read current of a memory array device is also disclosed.