Semiconductor Memory Repair Circuit Priority Logic
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in simultaneously performing repair operations for first and second sub-banks when failures occur in both, due to information collision during self-address rupture processes.
Innovation Solution
A semiconductor memory device with a repair circuit that includes a test data processing unit for generating fail detection signals, a repair address control unit for setting priority and selectively storing addresses, and a fuse unit for programming repair addresses, allowing for simultaneous repair operations by prioritizing bank groups and preventing address collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If self-address rupture is used for repair operations in multiple banks simultaneously, then repair efficiency is improved, but address collision occurs when failures occur in both first and second sub-banks
Solution Approach 1:
The patent applies preliminary action by setting priority levels for different bank groups before the repair operation occurs. The repair address control unit pre-configures priority information for first and second sub-banks, enabling it to automatically resolve address collisions by selecting addresses from higher-priority banks when both banks generate fail detection signals simultaneously. This preliminary configuration allows simultaneous repair operations without address collision errors.
Solution Approach 2:
The patent introduces an intermediary mechanism - the priority information and repair address control unit - that mediates between multiple banks during self-address rupture operations. When address collisions occur, this intermediary selectively controls which bank's addresses are latched and programmed, preventing conflicts while maintaining the efficiency of simultaneous operations across multiple banks.
2Reliability
If priority setting is implemented in repair address control, then address collision is prevented, but device complexity increases
Solution Approach 1:
The patent segments the bank group into first and second sub-banks with distinct priority levels. The repair address control unit is segmented to handle priority information separately for each sub-bank, processing fail detection signals and address selection in a modular fashion. This segmentation prevents address collisions while keeping each control module relatively simple and manageable.
Data Source
AI summary
A repair circuit includes a test data processing unit that outputs first and second fail detection signals using first and second test data of first and second memory banks, respectively, in response to a test mode signal, a repair address control unit that sets a priority of the first and second memory banks and selectively stores first and second addresses of the first and second memory banks based on the set priority in response to the first and second fail detection signals, and a fuse unit that performs repair programming based on the addresses selectively stored in the repair address control unit.