Memory Controller Outer-Cell Soft-Bit Decoding
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Solution Overview
Problem
Current semiconductor memory systems face challenges in improving the reliability of error correction processing due to variations in electrical characteristics and threshold voltage distributions across memory cell transistors, particularly distinguishing between outer and inner cells within the memory array.
Innovation Solution
The memory system employs a controller to generate outer-bit determination data, setting specific likelihood values for soft-bit data based on the location of memory cells within the array, enabling improved soft bit decoding and error correction by differentiating between outer and inner cells through optimal read voltage estimation and LLR value assignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform error correction is applied to all memory cells, then the error correction process is simple, but the correction capability is insufficient due to variations in electrical characteristics between outer and inner cells
Solution Approach 1:
The patent applies different error correction strategies to outer cells and inner cells based on their distinct electrical characteristics. Outer cells use one set of read voltages and LLR values while inner cells use another, optimizing correction capability for each region without requiring a completely different system architecture.
Solution Approach 2:
The memory array is segmented into outer cells and inner cells based on their position and electrical characteristics. The error correction process is divided into separate handling paths for each segment, allowing tailored decoding parameters for each region while maintaining overall system coherence.
2Measurement precision
If different read voltages are used for outer and inner cells, then the soft bit decoding accuracy is improved, but the read operation complexity increases
Solution Approach 1:
Different read voltages are applied locally to outer and inner cells according to their specific threshold voltage distributions. This allows optimal reading of each cell type while the controller manages the voltage selection automatically, hiding the complexity from the data processing layer.
Solution Approach 2:
The controller pre-determines which cells are outer cells and which are inner cells before reading, and pre-selects the appropriate read voltages accordingly. This preliminary classification and voltage assignment simplifies the subsequent reading process by eliminating the need for real-time voltage determination.
3Reliability
If location-based likelihood values are assigned, then the error correction capability is enhanced, but the control process becomes more complex
Solution Approach 1:
The controller performs preliminary identification of cell locations and assigns likelihood values before the error correction decoding process. This pre-processing of location information and likelihood assignment simplifies the main decoding operation by providing ready-to-use reliability metrics for each bit.
Solution Approach 2:
Location-based likelihood values serve as an intermediary between the physical cell location and the error correction decoding process. This intermediary layer translates spatial information into reliability metrics that can be directly used by the decoder, simplifying the overall control architecture.
Data Source
AI summary
According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.