Analog Bitscan Programming for Adaptive Memory Verify Control
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Solution Overview
Problem
Existing non-volatile memory programming techniques face inefficiencies in performance, reliability, and endurance due to limited output options in verify operations, leading to suboptimal programming parameters and increased error rates.
Innovation Solution
Implementing an analog bitscan operation that generates multiple output options (strong pass, weak pass, weak fail, and strong fail) to dynamically adjust programming parameters, such as voltage increments and loop counts, based on the output of each programming loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional binary verify operations are used in programming loops, then the programming process is simple to implement, but the programming precision and reliability are insufficient due to limited output options
Solution Approach 1:
The verify operation is segmented into multiple independent analog bitscan operations, each targeting specific threshold voltage ranges. This segmentation allows precise measurement of different memory cell states while maintaining modular implementation, resolving the contradiction between precision and complexity.
Solution Approach 2:
The verify operation transitions from binary (pass/fail) to multi-dimensional analog output levels. By introducing multiple output options corresponding to different threshold voltage ranges, the system achieves higher measurement precision while the dimensional expansion is managed through structured output categorization.
2Productivity
If fixed programming parameters are used across all programming loops, then the control logic is simple, but the programming efficiency and performance are suboptimal
Solution Approach 1:
Programming parameters are made dynamic rather than fixed. The analog bitscan output levels dynamically determine subsequent programming actions, allowing the system to adapt programming voltage, loop count, and verify thresholds based on real-time memory cell states, thereby improving efficiency while managing complexity through rule-based adaptation.
Solution Approach 2:
A feedback mechanism is implemented where analog bitscan results feed back into programming parameter selection. The multi-level output provides rich feedback information about programming progress and cell state, enabling optimized parameter adjustment that improves programming efficiency while the feedback structure remains systematic and manageable.
3Productivity
If aggressive programming pulses are applied to improve programming speed, then productivity increases, but reliability and endurance deteriorate due to increased error rates
Solution Approach 1:
Instead of applying uniformly aggressive programming pulses, the system applies partial action by adjusting pulse strength based on analog bitscan feedback. When memory cells are close to target threshold, weaker pulses are applied to avoid over-programming and errors, while stronger pulses are used when cells are far from target, optimizing both speed and reliability.
Solution Approach 2:
Programming parameters such as pulse voltage and duration are dynamically changed based on analog bitscan output levels. This parameter adaptation allows the system to maintain high programming speed when appropriate while preventing errors by adjusting parameters when cells approach target states, resolving the contradiction between speed and reliability.
Data Source
AI summary
The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program at least some of the plurality of memory cells of a selected word line of the plurality of word lines in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is also configured to determine an output of the analog bitscan operation. The output is one of at least three options. The circuitry is further configured to control at least one programming parameter based on the output of the analog bitscan operation.