Analog CAM Clause Search for Resource-Efficient SMT Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SMT solver accelerators, particularly those based on quadratic unconstrained binary optimization (QUBO), require excessive resources for solving large job-shop scheduling problems (JSSPs), making them inefficient for practical applications.
Innovation Solution
An SMT solver accelerator utilizing analog content addressable memory (CAM) cells to store and test expression clauses of a JSSP, employing a counter circuit and controller to iteratively refine input variables until a valid solution is found, leveraging analog CAM arrays and memristor technology for non-volatile memory and efficient search operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If QUBO-based SMT solver accelerators are used to solve large JSSPs, then the solving capability is achieved, but the resource requirements become excessively large
Solution Approach 1:
The patent replaces traditional digital computing mechanisms with analog CAM cell arrays to perform SMT solving. Instead of using digital logic circuits and sequential processing, the invention uses analog memory cells with continuous voltage levels to represent and evaluate variable assignments, enabling parallel evaluation of multiple clauses simultaneously and dramatically reducing resource requirements for large JSSP instances
Solution Approach 2:
The invention changes the parameter representation from discrete digital values to continuous analog voltage levels. Each CAM cell stores clauses with analog threshold values, and variable assignments are represented by analog voltages. This parameter transformation enables the system to evaluate satisfiability conditions through analog voltage comparisons rather than digital logic operations, reducing computational overhead and resource consumption
2Productivity
If traditional SMT solver accelerators are used, then solving functionality is provided, but efficiency is reduced due to excessive computational overhead
Solution Approach 1:
The patent merges multiple computational functions into a single analog CAM cell array structure. The same array that stores clause information is directly used for evaluation by applying input voltages corresponding to variable assignments. This merging eliminates the need for separate evaluation circuits and data transfer mechanisms, reducing device complexity and computational overhead while maintaining solving functionality
Solution Approach 2:
The analog CAM cell array serves multiple functions simultaneously: it stores clause definitions, performs threshold comparisons, evaluates satisfiability conditions, and produces output signals all within the same hardware structure. This multi-functionality reduces the overall device complexity compared to traditional accelerators that require separate dedicated circuits for each function
Data Source
AI summary
A satisfiability modulo theories (SMT) solver accelerator is implemented with analog content addressable memory (CAM) cells. A job-shop scheduling problem (JSSP) may be mapped to expression clauses that are stored in an analog CAM array. A test cycle may be performed by searching for a test vector of input variables in the analog CAM array, selecting a candidate variable of the test vector that is violating a largest number of the expression clauses, and changing the candidate variable of the test vector. The test cycle may be repeated until none of the expression clauses are violated by the test vector of the input variables. The resulting test vector of the input variables that violates no expression clauses is a solution for the JSSP.