Using amplifier gate capacitance and a biased MOSFET switch, this CMOS track-and-hold circuit pushes sampling beyond 6 GHz at lower cost.
A feedback amplifier and resistor network hold sample-and-hold common-mode voltage near Vref, countering leakage drift in AC-coupled ADC inputs.
A linear capacitor placed in parallel with MOS parasitics cuts input-dependent charge injection error and improves analog sampling accuracy.
A pass transistor and high-voltage gate drive clamp over-rail inputs so the sample-hold circuit avoids junction malfunction and holds signals accurately.