CMOS Track-and-Hold Circuit Using Gate Capacitance for 6 GHz Sampling
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Solution Overview
Problem
Track and hold circuits face limitations in sample rate due to the time required to charge the hold capacitor, especially when the sample rate exceeds 2-5 GHz, with silicon-based CMOS technology being cost-effective but insufficient for high-speed applications, and faster technologies like GaAs, SiGe, and InP/GaAs being costly.
Innovation Solution
The design incorporates a CMOS process with a 65-nanometer geometry, utilizing a p-channel MOSFET electronic switch and a dummy switch to reduce charge injection, along with a substrate bias signal and RC low-pass filter to minimize ON resistance and capacitance, enabling operation beyond 6 GHz by leveraging gate capacitance as the dominant storage capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a larger hold capacitor is used to reduce charging time, then the sample rate increases, but the circuit complexity and cost increase due to requiring faster technologies like GaAs, SiGe, or InP/GaAs
Solution Approach 1:
The patent changes the electrical parameters of the hold capacitor by utilizing the inherent gate capacitance of the buffer amplifier transistor rather than a separate physical capacitor. This parameter change allows achieving high sample rates (over 6 GHz) while remaining within CMOS technology constraints, avoiding the need for complex and expensive alternative technologies.
Solution Approach 2:
The patent merges the hold capacitor function with the buffer amplifier by using the gate capacitance of the buffer transistor as the hold capacitor. This consolidation eliminates the need for a separate hold capacitor component and reduces overall circuit complexity while maintaining high-speed performance.
2Productivity
If the hold capacitor capacitance is reduced to increase sample rate, then the charging time decreases, but the circuit becomes more sensitive to noise and signal integrity issues
Solution Approach 1:
By merging the hold capacitor with the buffer amplifier gate, the patent ensures that the holding capacitance is inherently coupled to the amplification function. This integration provides natural noise immunity and signal integrity protection while achieving high sample rates, as the buffer amplifier actively maintains signal quality during the hold phase.
3Ease of manufacture
If CMOS technology is used to maintain cost-effectiveness, then the manufacturing cost is reduced, but the maximum achievable sample rate is limited to below 5 GHz
Solution Approach 1:
The patent achieves a breakthrough in CMOS sample rate capability by changing how the hold capacitance is implemented. By using the gate capacitance of the buffer transistor and optimizing the switch and amplifier parameters, the circuit achieves over 6 GHz sample rate using standard CMOS technology, surpassing the traditional 5 GHz limit without requiring expensive alternative technologies.
4Productivity
If the ON resistance of the electronic switch is reduced to decrease charging time, then the sample rate increases, but the switch size increases and circuit complexity increases
Solution Approach 1:
The patent optimizes the switch parameters by carefully selecting the transistor width and length to achieve low ON resistance without excessive size. The switch is designed with specific dimensional parameters that balance resistance and area, enabling fast charging (high sample rate) while maintaining compact circuit area within CMOS constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-speed operation beyond 6 GHz while maintaining low power consumption and cost-effectiveness by optimizing switch and amplifier design, reducing charging time and increasing sample rate without the need for expensive alternative technologies.
Implementation Method 1
utilizing a parasitic capacitance as the dominant hold capacitance
Implementation Method 2
along with a substrate bias signal to reduce ON resistance
Data Source
AI summary
Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier.