Precision Sampling Circuit With Linearized Charge Injection
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Solution Overview
Problem
Existing sampling circuits for switched-capacitor filters and analog-to-digital converters suffer from nonlinear charge injection errors due to channel charge in MOS transistors, which are not adequately addressed by conventional ground-side sampling methods, especially in high-accuracy applications where second-order effects introduce significant nonlinearity.
Innovation Solution
The proposed sampling circuit incorporates a capacitor that is substantially more linear than the variable parasitic capacitance of the source-side transistor, connected in parallel to reduce the input-dependent charge injection error, and employs closed-loop and fully-differential configurations to minimize substrate and power supply noise, using operational or differential amplifiers to stabilize the charge sampling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ground-side sampling is used to remove input dependence of charge injection, then first-order nonlinear error is reduced, but second-order nonlinearity from impedance variation remains significant
Solution Approach 1:
A linear capacitor is introduced as an intermediary element connected in parallel with the parasitic capacitance of the source-side transistor. This linear capacitor serves as a mediator that dominates the total capacitance at the sampling node, thereby suppressing the effect of the nonlinear parasitic capacitance and impedance variation on charge injection accuracy.
Solution Approach 2:
The invention changes the parameter of capacitance linearity by introducing a capacitor with substantially higher linearity than the parasitic capacitance. By selecting a linear capacitor with appropriate capacitance value, the total capacitance becomes predominantly linear, reducing the second-order nonlinearity in charge injection even when source-side transistor impedance varies with input voltage.
2Ease of operation
If source-side transistor is used for sampling, then input voltage can be sampled directly, but nonlinear charge injection error occurs due to impedance variation
Solution Approach 1:
The linear capacitor acts as an intermediary that decouples the direct relationship between source-side transistor impedance variation and charge injection nonlinearity. By placing the linear capacitor in parallel, the sampling circuit maintains direct voltage sampling capability while the linear capacitor dominates the nodal capacitance, suppressing the harmful effect of transistor impedance variation.
3Device complexity
If conventional sampling circuit is used, then circuit complexity is low, but nonlinear charge injection errors significantly degrade sampling accuracy
Solution Approach 1:
The invention merges a linear capacitor with the existing parasitic capacitance of the source-side transistor by connecting them in parallel. This combination creates a total capacitance that is dominated by the linear capacitor's characteristics, thereby suppressing nonlinear charge injection errors while maintaining the simplicity of the original sampling circuit structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces nonlinear charge injection errors, enhances signal range, and improves noise rejection by maintaining a constant capacitance and resistance, thereby achieving higher accuracy in sampling analog voltages.
Implementation Method 1
A capacitor, which is substantially more linear than a variable parasitic capacitance of a source-side transistor, is connected in parallel to the variable parasitic capacitance to reduce an input-dependent charge injection error
Data Source
AI summary
A sampling circuit includes an input voltage source; a first switch having an input operatively connected to the input voltage source; a sampling capacitor operatively connected to an output of the first switch; an operational amplifier having an inverting input operatively connected to the sampling capacitor; a second switch operatively connected across the inverting input of the operational amplifier and an output of the operational amplifier; and a second capacitor operatively connected to the output of the first switch. The first switch has a variable parasitic capacitance, and the second capacitor has a substantially more linear capacitance than the variable parasitic capacitance and is in parallel with the variable parasitic capacitance. A combined variable parasitic capacitance and capacitance of said switch capacitor is more linear than the variable parasitic capacitance of the first switch.