Analog CAM SMT Solver for Resource-Efficient Job-Shop Scheduling
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Solution Overview
Problem
Existing SMT solver accelerators, particularly those based on quadratic unconstrained binary optimization (QUBO), require excessive resources for solving job-shop scheduling problems (JSSPs) with a large number of jobs/machines, making them inefficient.
Innovation Solution
An SMT solver accelerator utilizing analog content addressable memory (CAM) cells to store and test expression clauses of a JSSP, employing a counter circuit and controller to iteratively refine input variables until a solution is found that satisfies all clauses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If QUBO-based SMT solver accelerators are used to solve JSSPs with a large number of jobs/machines, then the solving capability is improved, but the resource requirements become excessively large
Solution Approach 1:
The patent replaces the conventional digital computing mechanism with an analog computing mechanism. Analog CAM cells use continuous voltage levels to represent binary states, enabling parallel evaluation of multiple clauses simultaneously. This substitution reduces the sequential processing overhead and resource consumption associated with QUBO-based digital solvers, allowing large-scale JSSPs to be solved with fewer physical resources.
Solution Approach 2:
The patent merges multiple clause evaluation functions into a single analog CAM cell structure. Each CAM cell integrates storage of clause information, comparison logic, and violation detection in one unified analog component. This consolidation eliminates the need for separate digital circuits for each function, significantly reducing the overall resource footprint when solving JSSPs with many jobs and machines.
2Reliability
If conventional SMT solver accelerators are used, then solving accuracy is maintained, but efficiency decreases due to excessive resource consumption
Solution Approach 1:
The patent substitutes digital binary logic with analog voltage-based logic while maintaining solving accuracy. The analog CAM cells use voltage threshold comparisons to determine clause satisfaction, providing deterministic results equivalent to digital logic. This substitution enables parallel processing of all clauses simultaneously, dramatically improving solving efficiency without sacrificing the reliability of the satisfiability determination.
Solution Approach 2:
The patent performs preliminary encoding of all SMT clauses into the analog CAM structure before the solving process begins. The clause information, variable assignments, and violation conditions are pre-configured in the analog memory cells, allowing the system to immediately evaluate any candidate solution without requiring extensive setup or initialization during the solving phase, thus improving overall efficiency.
Data Source
AI summary
A satisfiability modulo theories (SMT) solver accelerator is implemented with analog content addressable memory (CAM) cells. A job-shop scheduling problem (JSSP) may be mapped to expression clauses that are stored in an analog CAM array. A test cycle may be performed by searching for a test vector of input variables in the analog CAM array, selecting a candidate variable of the test vector that is violating a largest number of the expression clauses, and changing the candidate variable of the test vector. The test cycle may be repeated until none of the expression clauses are violated by the test vector of the input variables. The resulting test vector of the input variables that violates no expression clauses is a solution for the JSSP.