Analog Circuit Fault Feature Extraction Using Wavelet Embedding
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Solution Overview
Problem
Current fault feature extraction methods for analog circuits face challenges in accurately diagnosing single and multiple faults due to complex feature characteristics and overlapping sample categories, leading to poor diagnosis accuracy.
Innovation Solution
The method employs discrete wavelet packet transform to extract energy and kurtosis data from time-domain response signals, followed by parameter random distribution neighbor embedding winner-take-all dimensionality reduction using a multi-layer neural network based on restricted Boltzmann machines, to effectively separate fault features and reduce redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fault feature extraction methods are used, then feature extraction can be performed, but the separation of different fault features is poor and sample categories overlap significantly
Solution Approach 1:
The patent applies manifold learning to transform fault features from a high-dimensional space with poor separability to a low-dimensional embedded space where different fault categories are well-separated. This dimensional transformation resolves the contradiction by changing the representation space rather than modifying the features themselves, achieving both good separation and high diagnosis accuracy.
Solution Approach 2:
The patent changes the parameters of feature representation by learning optimal projection parameters through manifold learning. By adjusting the embedding dimensions and projection parameters, the method transforms features to maximize class separation while maintaining diagnostic reliability, directly addressing the poor separation issue without sacrificing accuracy.
2Adaptability or versatility
If more fault features are extracted to improve diagnosis coverage, then more fault types can be detected, but feature redundancy and interference increase
Solution Approach 1:
The patent extracts only the most discriminative fault features by embedding high-dimensional features into a lower-dimensional space. This extraction process removes redundant and interfering features while retaining the essential diagnostic information, achieving both comprehensive fault detection coverage and reduced feature complexity.
Solution Approach 2:
By transforming features from high-dimensional to low-dimensional space through manifold learning, the patent reduces feature redundancy while maintaining adaptability for detecting various fault types. The dimensional reduction eliminates interference from redundant features while preserving the versatility needed for comprehensive fault detection.
3Ease of operation
If conventional feature extraction methods are used, then the process is simple, but the handling of single-fault and multi-fault conditions is insufficient
Solution Approach 1:
The patent implements a universal manifold learning framework that handles both single-fault and multi-fault conditions through the same embedding process. The method universally transforms features regardless of fault type or combination, maintaining ease of operation while significantly improving the precision of feature differentiation across all fault scenarios.
Solution Approach 2:
The patent changes the feature space parameters through learned embedding transformations that adapt to different fault conditions. This parameter transformation maintains operational simplicity while enabling precise differentiation between single-fault and multi-fault features, resolving the contradiction between simplicity and precision.
Data Source
AI summary
An analog circuit fault feature extraction method based on a parameter random distribution neighbor embedding winner-take-all method, comprising the following steps: (1) collecting a time-domain response signal of an analog circuit under test, wherein the input of the analog circuit under test is excited by using a pulse signal, a voltage signal is sampled at an output end, and the collected time-domain response signal is an output voltage signal of the analog circuit; (2) applying a discrete wavelet packet transform for the collected time-domain response signal to acquire each wavelet node signal; (3) calculating energy values and kurtosis values of the acquired wavelet node signals to form an initial fault feature data set of the analog circuit; and (4) analyzing the initial fault feature data by the parameter random distribution neighbor embedding winner-take-all method, to acquire optimum low-dimensional feature data. The invention effectively reduces redundancy and interference elements in the fault features, and greatly improves degree of separation of different fault features and degree of polymerization of samples of same fault category.