Analog Semiconductor Circuit for Product-Sum and Activation Arithmetic

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor devices face challenges in performing product-sum operations and arithmetic operations of activation functions efficiently, leading to increased circuit area and power consumption.

Innovation Solution

A semiconductor device is designed with a configuration that includes multiple cells, current mirror circuits, and wiring connections, allowing for the performance of product-sum operations and activation function arithmetic with reduced power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If digital multiplication circuit and digital addition circuit with multi-bit arithmetic operation specifications are used, then the arithmetic operation accuracy is improved, but the circuit area and power consumption are increased

Engineering Contradiction:
Improvearithmetic operation accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent replaces digital multiplication and addition circuits with an analog circuit that performs product-sum operations using continuous voltage signals. The analog circuit uses operational amplifiers and resistors to compute weighted sums of input signals, eliminating the need for digital multipliers and adders. This substitution reduces circuit area and power consumption while maintaining arithmetic operation accuracy through the analog computation process.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Use of energy by moving object

If analog circuit is used for product-sum operation, then the circuit area and power consumption are reduced, but the signal conversion complexity is increased

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal conversion complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent designs the analog circuit to perform multiple functions including product-sum operations, activation function computations, and signal processing within a single integrated circuit. The operational amplifiers and resistor networks are configured to handle various neural network operations without requiring separate digital-analog conversion stages for each function, thereby reducing overall signal conversion complexity while maintaining low power consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If digital circuit is used for activation function arithmetic, then the computational precision is improved, but the circuit area is increased

Engineering Contradiction:
Improvecomputational precisionVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent replaces digital computation circuits with analog computational elements that perform activation function arithmetic using continuous voltage signals and operational amplifiers. The analog circuit uses nonlinear resistor networks and feedback mechanisms to compute activation functions such as sigmoid and tanh, achieving sufficient computational precision for neural network applications while occupying significantly less circuit area compared to digital implementations.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250054523A1Semiconductor device and electronic device
Publication Date: 2025.02.13 SEMICON ENERGY LAB CO LTD
  • US20250054523A1 patent drawing
  • US20250054523A1 patent drawing
  • US20250054523A1 patent drawing

AI summary

A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.