Computing Operations For Multiplication/Division TRIZ Cases

Multiple transistor-capacitor cells and a current mirror perform product-sum and activation arithmetic with lower area and power.

Current-mirror cells with transistors and capacitors cut signal-conversion overhead, reducing neural-network circuit area and power.

Phased depthwise and pointwise convolution on one CIM array cuts data movement, hardware overhead, cycle time, and power use.

A charge divider network scales and sums IMC column signals before one shared ADC, cutting ADC count, energy use, and quantization error.

Subthreshold analog circuits and energy monitoring enable edge vision computing on harvested power while maintaining stable, precise operation.

Using a FET in its linear region, this circuit performs analog multiplication or division with lower power and less complexity than DSP or Gilbert cells.

Harmonic-canceling square-wave multipliers approximate sine multiplication while widening input range and reducing temperature sensitivity.

A resistive memory array and reduction circuit compute VVDP sums in place, cutting memory access delay and power from data movement.

A 90-degree coupler and combiner suppress doubled-wave leakage, enabling stronger wideband tripled-wave output in a multiplier circuit.

Complementary parallel resistors and coordinated switches perform MAC operations in memory, cutting data movement power and boosting speed.

Vertical vias link switches to active variable resistors, enabling in-memory MAC operations with lower data movement and power use.

Embedded RNGs and DAC-equipped memory arrays run Bayesian neural inference locally, cutting data movement, latency, and edge energy use.

Pulse-length and voltage-amplitude encoding let a FET-capacitor circuit compute analog scalar products with far lower energy use in neural networks.

Power gating turns off unused non-volatile memory cells during CNN weighting computations, reducing power use while retaining needed data.

Winograd transforms reduce multiplication operations before analog matrix-vector multiplication, lowering convolution latency during CNN training on RPU arrays.

Combinatorial optimization faces slow searches among local optima; photonic crossbars evaluate multiple input vectors in parallel.

Replacing digital logic with an analog capacitor network reduces device complexity and power consumption while maintaining signal processing reliability.

Resistive memory crossbar arrays merge computation and storage to reduce energy consumption while improving area efficiency for neural network recall.

A programmable analog signal processing array uses pre-configurable slices with delay and multiplier elements to handle time-discrete operations.

A binary weight cell uses three NFETs and two MTJs to generate proportional output currents with transistor-level on/off ratios.

A semiconductor device accumulates electrical charge via paired input and gate units to perform analog arithmetic operations.

A memristive cross-bar array determines dot products by applying programming voltages to represent matrix values and collecting output currents.

A semiconductor addition method separates positive and negative data paths to prevent overflow during arithmetic operations.

A direct digital synthesis circuit uses logical multiplication to generate synthesized waveforms.

A frequency dependent input impedance circuit shapes readout pulses from solid state photomultipliers.

Applying dual voltage inputs to row electrodes minimizes signal degradation in memristive crossbar arrays.

Segmenting weight coefficients into separate nonvolatile storage elements reduces cell current while maintaining computational accuracy.

A memcapacitive cross-bar array performs dot product calculations using charge accumulation on capacitive memory devices.

An analog processing system computes iterative neural network models using vector-by-matrix multiplication circuitry and nonlinearity feedback loops.

Segmenting positive and negative value updates into two cycles reduces resistive processing unit update time while maintaining parallel operation.

A compute-in-memory bitcell merges storage and logic using cross-coupled inverters to process data in place.

A memristor crossbar array calculates linear transformations via vector-matrix multiplication.

A weight cell using bi-directional magnetic tunnel junction memory elements and diodes in a crossbar array architecture.

A memory crossbar array performs matrix-vector multiplications using programmable resistive elements and a dedicated readout circuit.

Resistive memory elements perform analog multiplication to sum multiple dot products, eliminating separate storage circuits.

Multi-bit semiconductor storage elements accumulate connection weight coefficients for neural network computation circuits.

A vector matrix multiplication accelerator executes Gaussian elimination using an analog resistive memory crossbar array to perform parallel row operations.

A programmable semiconductor device array performs analog vector-matrix multiplication by adjusting threshold voltages to define variable weights.