Computing Operations For Multiplication/Division TRIZ Cases
- Analog Semiconductor Circuit for Product-Sum and Activation Arithmetic
Multiple transistor-capacitor cells and a current mirror perform product-sum and activation arithmetic with lower area and power.
- Current-Mirror Semiconductor Circuit for Low-Power Product-Sum Arithmetic
Current-mirror cells with transistors and capacitors cut signal-conversion overhead, reducing neural-network circuit area and power.
- CIM Array Architecture for Phased Depthwise Convolution
Phased depthwise and pointwise convolution on one CIM array cuts data movement, hardware overhead, cycle time, and power use.
- Shared Column ADCs With Charge Summing for In-Memory Computing
A charge divider network scales and sums IMC column signals before one shared ADC, cutting ADC count, energy use, and quantization error.
- Subthreshold Analog Vision Computing With Energy-Aware Bias Control
Subthreshold analog circuits and energy monitoring enable edge vision computing on harvested power while maintaining stable, precise operation.
- FET Analog Arithmetic Circuit Using Linear-Region Multiplication
Using a FET in its linear region, this circuit performs analog multiplication or division with lower power and less complexity than DSP or Gilbert cells.
- Square-Wave Sine Multiplier With Harmonic Cancellation
Harmonic-canceling square-wave multipliers approximate sine multiplication while widening input range and reducing temperature sensitivity.
- Resistive Memory Array Reduction Circuit for In-Memory VVDP
A resistive memory array and reduction circuit compute VVDP sums in place, cutting memory access delay and power from data movement.