Resistive Memory Bitcell Layout for In-Memory MAC Computing
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Solution Overview
Problem
Neural network operations, such as multiply-accumulate (MAC) operations, are not efficiently performed using conventional hardware architectures other than digital computers, necessitating improved hardware for efficient memory access and computation.
Innovation Solution
A processing device with bitcells comprising active and inactive variable resistors, switches, and metal layers, including vias for connecting switches to active resistors, is designed to facilitate in-memory processing, enabling efficient MAC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional hardware architecture is used for neural network operations, then general-purpose computing is maintained, but MAC operation efficiency and power consumption are insufficient
Solution Approach 1:
The patent merges memory and processing functions into a single integrated structure where variable resistors store weights and switches perform computations in-place. This eliminates data movement between separate memory and processing units, achieving both high MAC operation efficiency and reduced power consumption by performing computations where data is stored.
Solution Approach 2:
The patent replaces conventional digital switching with analog variable resistors that continuously adjust resistance values to represent weights. This substitution enables efficient MAC operations through analog multiplication (current × resistance = voltage) and summation, significantly improving computational efficiency for neural network operations.
2Reliability
If more vias are added to connect switches and variable resistors, then electrical connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar 2D connections to 3D vertical connections using vias that penetrate through the variable resistor layer. This dimensional change enables direct vertical connections between switches in the active layer and variable resistors in the variable resistor layer, improving connection reliability while maintaining manufacturability through standard semiconductor fabrication processes.
3Area of stationary object
If variable resistors are densely packed in the variable resistor layer, then device area is reduced, but connection precision between switches and variable resistors deteriorates
Solution Approach 1:
The patent uses vertical vias to penetrate through the variable resistor layer, enabling precise 3D alignment between switches and variable resistors. This vertical connection approach allows dense packing of variable resistors in the horizontal plane while maintaining precise electrical connections through the vertical dimension, overcoming the trade-off between area and precision.
Solution Approach 2:
The via structure acts as an intermediary element that bridges the gap between switches and variable resistors. By introducing this intermediate connection component, the patent enables precise electrical connections even when switches and variable resistors are densely packed, as the via provides a dedicated vertical pathway for current flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device enables efficient in-memory processing by allowing symmetrical and parallel operations of bitcells, enhancing the performance of neural network computations.
Implementation Method 1
Each of the active variable resistors may be a magnetic tunnel junction device
Implementation Method 2
an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors
Implementation Method 3
at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors
Data Source
AI summary
A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.