Current-Mirror Semiconductor Circuit for Low-Power Product-Sum Arithmetic
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Solution Overview
Problem
In artificial neural networks, the combination of digital and analog circuits for product-sum operations and activation functions leads to increased circuit area and power consumption due to repeated signal conversions between digital and analog signals, complicating the implementation of efficient arithmetic operations.
Innovation Solution
A semiconductor device comprising cells with transistors and capacitors, along with current mirror and subtraction circuits, that perform product-sum operations and activation function arithmetic with reduced power consumption by optimizing current flow and signal conversion within the circuit architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital multiplication and addition circuits are used to perform product-sum operations with multi-bit arithmetic specifications, then calculation accuracy is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent merges multiple digital circuits (multiplication circuits and addition circuits) into a single integrated circuit that performs product-sum operations. This consolidation reduces the total circuit area while maintaining multi-bit arithmetic capabilities and calculation accuracy through shared computational resources and optimized data flow paths.
Solution Approach 2:
The integrated circuit is designed to perform multiple functions including multiplication, addition, and product-sum operations within a single device. This multi-functionality eliminates the need for separate dedicated circuits for each operation, thereby reducing overall circuit area while preserving computational precision through unified architectural design.
2Measurement precision
If digital multiplication and addition circuits are used to perform product-sum operations with multi-bit arithmetic specifications, then calculation accuracy is improved, but power consumption increases
Solution Approach 1:
By combining multiplication and addition functions into a single integrated circuit, the patent reduces the total number of active components and interconnections. This merger decreases dynamic power consumption from switching activities and static power consumption from leakage currents, while maintaining multi-bit arithmetic precision through coordinated operational units.
Solution Approach 2:
The universal circuit design performs multiple arithmetic operations using shared computational resources, reducing the overall power consumption compared to having separate dedicated circuits. The unified architecture enables efficient resource utilization and reduces redundant power consumption while preserving calculation accuracy across different operational modes.
3Area of stationary object
If analog circuits are used for product-sum operations, then circuit area and power consumption are reduced, but signal conversion between analog and digital increases complexity
Solution Approach 1:
The patent replaces analog circuit operations with digital circuit operations, eliminating the need for analog-to-digital and digital-to-analog conversions. This substitution maintains the area and power efficiency benefits of analog designs while avoiding the complexity of signal conversion interfaces, achieving both compact integration and computational precision through purely digital implementation.
Data Source
AI summary
A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.