Programmable Analog Signal Processing Array for Time-Discrete Operations
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Solution Overview
Problem
Existing programmable analog signal processing arrays face limitations in flexibility and efficiency due to their reliance on digital logic cell automata, which restricts their ability to effectively process analog signals with varying amplitudes and requires increased hardware for higher signal resolution.
Innovation Solution
A programmable analog signal processing array comprising a network of pre-configurable processing slices with switchable clock inputs, delay elements, analog multipliers, adder elements, and resample elements, allowing for time-discrete processing and flexible configuration of signal flow, enabling efficient processing of analog signals without the need for additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital logic cell automata are used for analog signal processing, then the system can be programmed and reconfigured, but the flexibility to process analog signals with varying amplitudes is restricted and additional hardware is required for higher signal resolution
Solution Approach 1:
The patent replaces digital logic operations with continuous analog circuit operations. Analog multipliers, adders, and delay elements process signals continuously in the analog domain, eliminating the need for digital conversion and processing steps. This substitution of analog mechanisms for digital ones enables direct processing of analog signals with varying amplitudes while maintaining programmability through configuration of circuit parameters
Solution Approach 2:
The patent employs programmable analog processing slices where circuit parameters such as multiplication factors, addition weights, and delay times can be configured to implement different signal processing functions. By changing these parameters rather than reconfiguring the entire hardware architecture, the system achieves flexibility to process different analog signal types and resolutions without adding hardware complexity
2Productivity
If digital logic cell automata are used, then programmability is achieved, but processing efficiency for time-discrete analog signals is reduced
Solution Approach 1:
The patent substitutes analog circuit mechanisms for digital logic operations. Continuous analog multiplication, addition, and delay operations occur simultaneously in parallel across multiple processing slices, providing time-discrete processing capability inherent to analog circuits while maintaining programmability through configurable circuit parameters
Solution Approach 2:
The patent divides the analog signal processing system into multiple identical processing slices, each capable of independent operation. This segmentation allows parallel processing of multiple signal streams or different processing stages, improving overall productivity while each slice remains programmable through configuration of its internal analog components
Data Source
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AI summary
A programmable analog processing array for programmable time-discrete processing of analog input signals in accordance with a desired signal processing function comprises a network of mutually interconnectable and pre-configurable analog processing slices that form unit circuit cells of the network. Each processing slice comprises a set of cell circuit elements including: a switchable clock input port for receiving a clock signal, a delay element for receiving a respective analog slice input signal and for forwarding the received slice input signal with a pre-configurable time delay as a respective delayed slice input signal, an analog multiplier element receiving the delayed slice input signal for providing an analog multiplier output signal corresponding to a product of the delayed slice input signal with a pre-configurable multiplication factor, an analog adder element receiving a pre-configurable selection of at least two adder input signals including the multiplier output signal and for providing an analog adder output signal corresponding to a sum of the adder input signals, and including an analog resample element for receiving the adder output signal and for providing the received adder output with a pre-configurable time delay as an analog slice output signal.