Resistive Memory Array Reduction Circuit for In-Memory VVDP
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Solution Overview
Problem
Computing devices face significant memory access delays and high power consumption when performing large numbers of Vector-Vector Dot-Product (VVDP) computations due to the high number of memory accesses required, which can overwhelm the system.
Innovation Solution
A computing device programmable media that includes a resistive element array and a reduction circuit, allowing VVDP computations to be performed directly in the media without moving data between memory and processing units, by programming resistive elements with weight values and applying drive voltages based on input vectors to calculate reduction values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If VVDP computations are performed using traditional memory-access methods, then computation can be done with standard processing units, but memory access delays and power consumption increase substantially
Solution Approach 1:
The patent merges memory and processing functions into a single integrated device. The resistive element array serves both as memory storage and as the computational element, eliminating the need to transfer data between separate memory and processing units. This integration directly reduces power consumption from data transfers while maintaining high computation efficiency through in-situ VVDP calculations.
Solution Approach 2:
The patent introduces a specialized resistive element array as an intermediary structure that enables direct computation within the memory array. This intermediary structure allows voltage inputs to be transformed into current outputs through resistive elements, performing dot-product calculations without requiring data to leave the memory array, thus reducing power consumption while maintaining productivity.
2Loss of time
If VVDP computations are performed with standard processing units, then system architecture remains simple, but memory access delays create high computing load
Solution Approach 1:
The patent combines memory storage and computational processing into a single resistive element array structure. By integrating both functions in one device, the system eliminates memory access delays while the specialized structure handles the complexity of in-situ computation, effectively reducing time loss without requiring complex multi-component system architecture.
Solution Approach 2:
The patent replaces the traditional mechanical/electrical data transfer process between separate memory and processing units with a direct electrical computation process within the resistive element array. Voltages applied to the resistive elements directly produce computational results through physical electrical phenomena, eliminating the time-consuming data transfer step while using well-understood electrical principles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces memory access delays and power consumption by performing VVDP calculations within the resistive element array, enabling efficient computation of reductions without the need for data transfer between memory and processing units.
Implementation Method 1
a plurality of programmable resistive elements coupled between the plurality of word lines and the plurality of bit lines
Data Source
AI summary
Devices for computing the sum of multiple Vector-Vector Dot-Products (VVDP) or multiple partial sums of VVDP can include a resistive memory array and a reduction circuit. The reduction circuit can be configured to determine a sum of a selected one or more of a plurality of bit lines of the resistive memory array. A VVDP reduction can be determined from the sum of the selected one or more of the plurality of bit lines.