Signed Integer Addition Circuit for Semiconductor Power Reduction

Solution Overview

Problem

Existing semiconductor devices face challenges in reducing power consumption and circuit scale while maintaining arithmetic processing capability, particularly in AI applications like deep learning where signed floating-point data processing leads to increased logical scale and power consumption.

Innovation Solution

A signed integer addition method is implemented using a semiconductor device with a memory structure that supplies data with positive and negative signs to separate memories, allowing for efficient addition and overflow prevention, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If signed floating-point data is processed with digital arithmetic operation, then arithmetic processing capability is improved, but logical scale increases and power consumption increases

Engineering Contradiction:

Improvearithmetic processing capabilityVSAvoidlogical scale

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent changes the data representation parameter from signed floating-point format to signed integer format. This parameter change simplifies the arithmetic operations required, reducing the logical scale of the circuit while maintaining arithmetic processing capability for AI applications such as neural network computations.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent segments the addition operation into separate processing paths for positive numbers and negative numbers. By dividing the computation into distinct segments handled by different circuits (positive number addition circuit and negative number addition circuit), the overall logical scale is reduced compared to a general-purpose floating-point addition unit.

Inventive Principle:

Principle #1Segmentation

2Productivity

If signed floating-point data is processed with digital arithmetic operation, then arithmetic processing capability is improved, but power consumption increases

Engineering Contradiction:

Improvearithmetic processing capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent changes the data representation parameter from signed floating-point format to signed integer format. This parameter change simplifies the arithmetic operations required, reducing the logical scale of the circuit while maintaining arithmetic processing capability for AI applications such as neural network computations.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent segments the addition operation into separate processing paths for positive numbers and negative numbers. By dividing the computation into distinct segments handled by different circuits (positive number addition circuit and negative number addition circuit), the overall logical scale is reduced compared to a general-purpose floating-point addition unit.

Inventive Principle:

Principle #1Segmentation

3Area of stationary object

If circuit scale is reduced to store in narrow space, then device size is reduced, but arithmetic processing capability may decrease

Engineering Contradiction:

Improvedevice sizeVSAvoidarithmetic processing capability

Core Design Contradiction:

Area of stationary objectVSProductivity

Solution Approach 1:

The patent segments the addition operation into separate processing paths for positive numbers and negative numbers. By dividing the computation into distinct segments handled by different circuits (positive number addition circuit and negative number addition circuit), the overall logical scale is reduced compared to a general-purpose floating-point addition unit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the data representation parameter from signed floating-point format to signed integer format. This parameter change simplifies the arithmetic operations required, reducing the logical scale of the circuit while maintaining arithmetic processing capability for AI applications such as neural network computations.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250068391A1Addition method, semiconductor device, and electronic device

Publication Date: 2025.02.27 SEMICON ENERGY LAB CO LTD

AI summary

A multiplier circuit includes a first circuit comprising a first transistor, a second transistor, a first capacitor, and a second capacitor. It further includes a second circuit comprising a third transistor, a fourth transistor, a third capacitor, and a fourth capacitor.