Binary Weight Cell Using MTJs and FETs for High On/Off Ratio
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Solution Overview
Problem
Current hardware accelerators for machine learning applications face inefficiencies in matrix vector multiplications due to the large size and power inefficiency of static random access memory, as well as low on/off ratios and high variation in nonvolatile memory options like RRAM and STT-MRAM.
Innovation Solution
A binary weight cell configuration using two magneto tunnel junctions (MTJs) and three N-type field effect transistors (NFETs) with a polysilicon load resistor, which enhances the on/off ratio of resistive memory devices and reduces output current magnitude and variation, allowing for efficient semi-digital matrix vector multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nonvolatile memory options (RRAM, FLASH, STT-MRAM) are used for weight representation, then memory density and non-volatility are improved, but on/off ratio and programming voltage compatibility deteriorate
Solution Approach 1:
The weight cell is segmented into multiple functional components: two MTJs for weight storage, three FETs for signal control and amplification, and a load resistor for current generation. This segmentation allows each component to perform its specific function optimally, with the FETs providing transistor-level on/off ratios independent of the MTJ's inherent on/off ratio limitations.
Solution Approach 2:
The FETs act as intermediary elements between the MTJs and the output current. The MTJs store weight information in their resistance states, but the FETs amplify and convert these states into proportional output currents with high on/off ratios, serving as a mediator that transforms the limited MTJ on/off ratio into the desired high on/off ratio output.
2Quantity of substance
If resistive memory devices are used for weight representation, then non-volatility and density are improved, but output current variation and programming voltage compatibility deteriorate
Solution Approach 1:
The circuit changes the operating parameters by using FETs to generate output currents proportional to the MTJ resistance states. Instead of directly reading current from the MTJs (which would show high variation), the FETs transform the resistance states into controlled current outputs with reduced variation, achieving precision despite manufacturing variations in the resistive memory devices.
3Speed
If SRAM is used for weight representation, then speed and accessibility are improved, but area and power consumption deteriorate
Solution Approach 1:
The circuit merges the weight storage function (MTJs) with the signal generation function (FETs and load resistor) into a single integrated weight cell. This combination eliminates the need for separate SRAM cells, reducing the overall area while maintaining fast access speeds through the direct analog signal generation capability of the FET-based circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The binary weight cell achieves a high on/off ratio for output current, matching that of transistors, and limits output current variation, enabling efficient parallel reads during inference with reduced power consumption.
Implementation Method 1
two magneto tunnel junctions (MTJs) and three N-type field effect transistors (NFETs) with a polysilicon load resistor
Implementation Method 2
three N-type field effect transistors (NFETs) with a polysilicon load resistor
Data Source
AI summary
A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.