Semiconductor Device Charge Accumulation Parasitic Capacitance

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Solution Overview

Problem

Current analog computing systems face challenges in reducing energy consumption due to parasitic capacitance in wiring, which increases energy consumption as the scale of the computing array grows, limiting further energy efficiency improvements.

Innovation Solution

The proposed semiconductor device includes an input unit, a computing unit with an accumulation unit connected to multiple pairs of input and gate units, and an output unit, where the computing unit accumulates charges from the input units via variable resistors and switches, allowing for efficient charge transfer and detection, reducing energy consumption by minimizing parasitic capacitance effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the scale of the computing array is increased to improve processing capability, then productivity is improved, but energy consumption increases due to parasitic capacitance in wiring

Engineering Contradiction:
Improveprocessing capabilityVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the computing array into multiple independent computing units, each with its own accumulation unit. This segmentation allows each unit to operate independently with minimized wiring, thereby reducing parasitic capacitance effects while maintaining overall processing capability through parallel operation of multiple units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar wiring layouts to a three-dimensional stacked architecture where accumulation units are positioned vertically above input units. This dimensional change reduces the horizontal wiring distance and parasitic capacitance while enabling higher density computing arrays with improved productivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If conventional analog computing architecture is used, then device complexity is low, but energy consumption increases due to parasitic capacitance effects

Engineering Contradiction:
Improvearchitecture complexityVSAvoidenergy waste
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent introduces accumulation units as intermediary components between input units and output units. These accumulation units serve as local charge storage elements that minimize the need for long-distance charge transfer, thereby reducing parasitic capacitance effects and energy waste while maintaining a relatively simple overall architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces conventional voltage-based analog computing with a charge-based computing system using floating body transistors. This substitution eliminates the need for high-precision voltage wiring and reduces parasitic capacitance effects, achieving lower energy waste with only moderate increases in device complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables reduced energy consumption by separating charge accumulation and detection functions, allowing for lower voltage operation and reduced energy waste, enabling more efficient analog product-sum operations compared to existing technologies.

Implementation Method 1

a computing unit that accumulates a charge from the input unit and performs an arithmetic operation

Methodology Applied
Scientific EffectCharge transfer: Conduction (electrical)

Data Source

PatentUS20230409843A1Semiconductor device
Publication Date: 2023.12.21 SONY GROUP CORP
  • US20230409843A1 patent drawing
  • US20230409843A1 patent drawing
  • US20230409843A1 patent drawing

AI summary

The present disclosure relates to a semiconductor device capable of reducing energy consumption.Provided is a semiconductor device including: an input unit that inputs a charge; a computing unit that accumulates a charge from the input unit and performs an arithmetic operation; and an output unit that detects and outputs the charge accumulated in the computing unit, in which the computing unit includes an accumulation unit to which a plurality of pair units, each of which is a pair of the input unit and a gate unit, is connected, each of the plurality of pair units makes a charge input from the input unit to the accumulation unit variable, and the accumulation unit accumulates a charge input from each of the connected plurality of pair units. The present disclosure is, for example, applicable to an analog computing device.