Parallel Resistive Bitcell Circuit for In-Memory MAC Computing
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Solution Overview
Problem
Existing neural network operations, such as multiply-accumulate (MAC) operations, are not efficiently performed using conventional hardware architectures other than digital computers, and there is a need for more efficient hardware solutions.
Innovation Solution
A bitcell circuit comprising a pair of variable resistors connected in parallel, each set with complementary resistance values and controlled by switches, is used to perform MAC operations, mimicking neuromorphic computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional digital computer hardware architecture is used to perform MAC operations, then the device complexity is well-defined, but the processing efficiency and speed for neural network operations are insufficient
Solution Approach 1:
The patent replaces traditional digital computer mechanical/electronic switching systems with a neuromorphic processing system that uses variable resistors to perform MAC operations. The resistive memory devices directly encode weights as resistance values, eliminating the need for complex digital arithmetic circuits and enabling parallel analog computation of neural network operations.
Solution Approach 2:
The patent changes the fundamental parameter representation from digital binary values to continuous resistance values. By mapping weights to resistance values of variable resistors and inputs to voltage levels, the system performs multiplication through Ohm's law (I=V/R) and accumulation through parallel current summation, fundamentally altering how computational parameters are represented and processed.
2Speed
If resistive memory devices are used for in-memory processing, then the data transmission speed and processing efficiency are improved, but the power consumption may increase
Solution Approach 1:
The patent merges the storage and processing functions into a single in-memory computing architecture. By performing MAC operations directly within the resistive memory array without transferring data between separate memory and processing units, the system eliminates data movement energy overhead while maintaining high processing speed through parallel analog computation.
Solution Approach 2:
The patent employs periodic switching of transistors to control variable resistors during MAC operations. The switches are activated in coordinated periodic cycles to select specific resistors for computation, enabling time-multiplexed operation that reduces overall power consumption while maintaining high effective processing throughput through efficient use of switching events.
3Measurement precision
If variable resistors with complementary resistance values are used in parallel, then the MAC operation accuracy is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent implements feedback mechanisms where the actual resistance values of variable resistors are measured and used to adjust subsequent computations. By reading back the resistance values and compensating for manufacturing variations through calibration data stored in the system, the architecture achieves high MAC operation accuracy despite variations in initial resistor fabrication tolerances.
Solution Approach 2:
The patent transforms the precision problem by changing from requiring precise fixed resistance values to using programmable variable resistors whose effective resistance can be dynamically adjusted. The complementary resistance value approach (using R and 1/R relationships) provides mathematical compensation that reduces the impact of manufacturing variations on final computation accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient in-memory processing of neural network operations, reducing power consumption and enhancing data transmission speed by performing MAC operations directly in memory.
Implementation Method 1
a first variable resistor as a resistive memory device having a resistance value that is set based on the resistive memory device switching between different resistance states
Implementation Method 2
a first switch serially connected to the first variable resistor and configured to switch application of a voltage or current to the first variable resistor
Data Source
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AI summary
A bitcell circuit includes: a first variable resistor as a resistive memory device having a resistance value that is set based on the resistive memory device switching between different resistance states; a second variable resistor as another resistive memory device connected to the first variable resistor in parallel, wherein the second variable resistor is set with a resistance value complementary to the resistance value of the first variable resistor; a first switch serially connected to the first variable resistor and configured to switch application of a voltage or current to the first variable resistor; and a second switch serially connected to the second variable resistor and configured to perform a switching operation for applying the voltage or current to the first variable resistor, complementarily to the first switch.