Parallel Analog Circuit Simulation with Pre-calculated Overlap Time
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Solution Overview
Problem
Existing parallel circuit simulation techniques for EDA tools are inefficient for smaller circuit designs due to the time-consuming process of determining the appropriate overlap time (Tov) for transient simulations, which is necessary to account for memory effects in analog circuits.
Innovation Solution
Determine the overlap time (Tov) based on the time required for output signals of an analog circuit to settle to a steady state, segment the simulation time into equal segments, overlap adjacent segments by Tov, simulate these segments in parallel, and truncate all but the first intermediate results to merge into a final simulation result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel circuit simulation techniques are used to reduce simulation time, then simulation speed is improved, but the technique is not beneficial for smaller circuit designs due to the time-consuming iterative process to determine overlap time
Solution Approach 1:
The patent applies preliminary action by pre-calculating the overlap time period Tov using a simplified formula based on circuit parameters (Tov = k × τ, where τ is the circuit time constant) before the actual parallel simulation begins. This eliminates the need for time-consuming iterative processes during the simulation setup phase, allowing smaller circuit designs to benefit from parallel simulation techniques without suffering from excessive overlap time determination overhead.
2Measurement precision
If iterative algorithms are used to determine overlap time Tov, then accuracy of memory effect accounting is improved, but the process becomes time consuming
Solution Approach 1:
The patent changes the approach from iterative parameter adjustment to direct parameter calculation. Instead of iteratively adjusting Tov to achieve convergence, the method directly calculates Tov using the formula Tov = k × τ, where k is a predetermined constant and τ is the circuit time constant. This parameter change maintains sufficient accuracy for memory effect accounting while eliminating the iterative time overhead.
Data Source
AI summary
A system and method are provided that reduce the amount of time required to perform transient circuit and envelope transient circuit simulations. The total simulation time is partitioned into n simulation segments of equal lengths of time and adjacent simulation segments are overlapped in time by a predetermined overlap time period, Tov. The simulation segments are then simulated in parallel and the simulation results are merged into a final simulation waveform. The predetermined overlap time period Tov is determined using a non-iterative process that can be performed very quickly. Consequently, the overall amount of time that is required to perform the simulation is greatly reduced.