Computer Aided Design TRIZ Cases
- Multi-pass Fill and Cheese Structure Design for CMP Flatness
Multi-pass method generates fill patterns with forbidden areas to constrain structural placement during circuit layout.
- Dynamic Programming Track Assignment for Circuit Routing
Dynamic programming identifies breaking points to assign tracks, reducing blockage violations and wire overlap in circuit designs.
- 3D Routing Optimization for VLSI Signal Integrity and RC Properties
Dynamic 3D routing adjusts wire traits to enhance signal integrity.
- Automatic Clock Routing in ASICs Using Standardized Grid
Standardized clock buffer grid automatically routes signals across application specific integrated circuit partitions.
- Dummy Boundary Cells for Layout Compliance and Chip Area Reduction
Standard dummy boundary cells form rings around functional circuits, reducing chip area while maintaining strict design rule compliance.
- Macro Cell Alignment via Virtual Power Grid
Generating a virtual power grid from a reference macro automates alignment, resolving manual precision issues in IC design.
- Hierarchical Power Verification System for SoC Memory Optimization
Abstract module models replace detailed internal structures, reducing memory footprint and verification time during hierarchical SoC analysis.
- Circuit Design Layout Pattern Error Identification
Identifies short circuit locations by assigning IDs to layout designs, resolving imprecise LVS tool highlighting.
- Computational Accelerator for MBSE Change Control
A computational accelerator segments model statements to propagate changes based on linkage strength.
- Analog Circuit Simulator Event-Driven Verification
Analog circuit simulator converts voltage and current variables into time functions for simulation.
- Automated Double Patterning Loop Violation Detection in IC Layouts
Graph tracing and breadth-first search identify double patterning loop violations in integrated circuit design layouts.
- IC Extraction Using Halo-Based Granular Segmentation
Halo-based segmentation isolates modified design regions for targeted re-extraction, eliminating computational waste from processing unchanged sections.
- Automated EDA Tool for Stacked Die Interconnect Verification
This verification system corrects microbump mapping discrepancies between stacked dies, reducing debugging time and eliminating manual error-prone inspection processes.
- Global Interconnect Inductance Estimation for Accurate RLC Modeling
Estimating inductance from parallel and non-parallel wires generates accurate RLC models, resolving signal propagation delay inaccuracies in wide interconnects.
- Circuit Layout Congestion Prevention via Virtual Blockages
A circuit layout apparatus analyzes routing congestion and disposes virtual blockages to reserve space for device placement.
- Trim Data Representation Using Adjacent Object Attributes
Existing layout objects include gap shape attributes to derive properties without separate gap objects.
- Semiconductor Pin Routing Automation via Net List Generation
A design system generates net lists from candidate pins to automate routing between semiconductor device elements.
- Integrated Circuit Power Optimization via Graph-Based Move Selection
A graph-based engine selects discrete component modifications to reduce integrated circuit power consumption.
- FinFET Bias Temperature Instability Prediction via Transient Simulation
Discrete time-step analysis captures state-dependent degradation recovery in FinFET devices, overcoming the accuracy limits of simple mathematical models.
- Integrated Circuit Aging Estimation via Hierarchical Netlist Simulation
A circuit simulation system calculates integrated circuit aging parameters using embedded measurement commands within a process design kit.
- Parallel Analog Circuit Simulation with Pre-calculated Overlap Time
A parallel simulation method segments analog circuit time into overlapping intervals processed concurrently to reduce transient analysis duration.