Dummy Boundary Cells for Layout Compliance and Chip Area Reduction
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Solution Overview
Problem
The integration of complex integrated circuits is complicated by the varied boundary shapes of functional cells and stringent design rules, which can lead to inefficiencies in layout design and space utilization during the electronic design automation (EDA) process.
Innovation Solution
The use of dummy boundary cells with predetermined structures, such as standard dummy friendly boundary cells (DFBCs), which are placed around functional cells to form a ring, facilitating a predictable layout environment and allowing for sharing between adjacent cells, thereby simplifying the integration process and optimizing space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy boundary cells are placed around functional cells to meet design rules, then layout compliance is improved, but chip area increases
Solution Approach 1:
Adjacent functional cells share common dummy boundary cells at their interfaces. The dummy cells placed between two functional cells serve both cells simultaneously, reducing redundant dummy cell placement and minimizing the additional chip area required while ensuring both cells meet design rule requirements.
Solution Approach 2:
Dummy boundary cells are designed with standardized structures that can be universally applied to different functional cell types and boundary configurations. These standardized dummy cells serve multiple purposes: meeting design rules, providing consistent spacing, and enabling predictable layout environments across the entire chip design.
2Adaptability or versatility
If varied boundary shapes of functional cells are accommodated, then design flexibility is improved, but integration complexity increases
Solution Approach 1:
The boundary of each functional cell is segmented into discrete segments that can be independently handled. Dummy boundary cells are placed along these segmented boundaries in a systematic manner, breaking down the complex problem of handling varied boundary shapes into manageable, repeatable units that simplify the integration process.
Solution Approach 2:
The approach transforms the variable parameter of boundary shape into a standardized parameter set by using predetermined dummy cell structures. By changing the parameters of the dummy cells (their standardized dimensions and placement rules) rather than adapting to each unique boundary shape, the integration complexity is reduced while maintaining design flexibility.
3Manufacturing precision
If standard dummy friendly boundary cells are used, then layout predictability is improved, but space utilization decreases
Solution Approach 1:
Adjacent functional cells share common dummy boundary cells at their interfaces. This sharing mechanism reduces the total number of dummy cells required across the chip, thereby improving space utilization while maintaining the layout predictability that standardized dummy cells provide for each individual cell.
Data Source
AI summary
Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.