Hierarchical Power Verification System for SoC Memory Optimization
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Solution Overview
Problem
The increasing complexity of System on Chip (SoC) designs leads to prolonged verification times and high memory requirements in power verification, making it challenging for developers to complete power verification within the tight timeline before tape-out.
Innovation Solution
The Hierarchical Power Verification System (HPVS) uses abstract models to simplify module definitions, reducing the need for internal module details while providing sufficient information for higher-level power verification, thereby reducing verification time and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full verification of entire SoC design is performed, then verification completeness is improved, but verification time increases
Solution Approach 1:
The verification process is divided into hierarchical levels where modules are verified individually first, then grouped into subsystems, and finally integrated into the complete SoC. This segmentation allows verification to be performed in manageable chunks rather than requiring complete design verification at once, thus reducing overall verification time while maintaining completeness.
Solution Approach 2:
Modules are verified in advance before being integrated into the complete SoC design. The verification tool generates abstract models of verified modules that can be reused in higher-level verification, eliminating the need to re-verify already-checked portions and significantly reducing total verification time.
2Reliability
If full verification of entire SoC design is performed, then verification completeness is improved, but memory requirements increase
Solution Approach 1:
Instead of loading and processing the entire SoC design simultaneously, the verification tool creates abstract models (copies) of individual modules after verification. These abstract models contain only the essential verification information needed for higher-level checks, dramatically reducing memory requirements while still enabling complete verification through hierarchical composition.
3Measurement precision
If detailed module definitions are used, then verification accuracy is improved, but verification speed decreases
Solution Approach 1:
The verification approach uses detailed module definitions only where necessary for accurate verification of specific modules, while using abstract models for higher-level verification where full detail is not required. This local application of detail versus abstraction optimizes both accuracy and speed by applying computational resources only where precision is critical.
Data Source
AI summary
A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. Design blocks are replaced with these abstract power models, resulting in reduced run-time and memory requirements. The power models can include power switches inside the block, related supplies of logic ports, supply power states, system power states, power management devices such as isolation logic and level shifters, feed-through and floating ports. The power model may be expressed either in UPF or as a combination of liberty model and UPF. After replacing modules with abstracted models the HPVS can quickly verify an entire SoC with a small memory footprint. When a user modifies a module, the HPVS need only verify the changed module and related modules at higher levels of module hierarchy.