Statistical Timing Model for Integrated Circuit Design
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Solution Overview
Problem
Current static timing analysis methods, particularly corner-based approaches, fail to accurately capture process variations in integrated circuit manufacturing, leading to overly conservative or optimistic designs and inefficiencies due to exponential computational complexity, and do not effectively account for intradie variations, which are significant in nanometer technologies.
Innovation Solution
The method involves creating a statistical timing model that uses a timing graph with statistical functions for delay, slew, and arrival time, allowing for the merging of timing arcs to reduce the graph, thereby simplifying computations and improving the accuracy of timing analysis by considering the distribution of process parameters and their variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If corner-based static timing analysis is used to account for process variations, then timing analysis coverage is improved, but computational complexity increases exponentially
Solution Approach 1:
The patent segments the timing analysis problem by separating the statistical parameter generation from the timing analysis execution. It divides the process into: (1) generating statistical process parameters with their correlations, (2) performing timing analysis with these parameters, and (3) aggregating results to compute yield. This segmentation allows the use of fewer corner cases while maintaining statistical accuracy, thereby reducing computational complexity from exponential to polynomial scale.
Solution Approach 2:
The patent transforms the traditional corner-based deterministic parameters into statistical parameters that include mean, standard deviation, and correlation coefficients. By changing from fixed corner values to distributed statistical parameters, the method captures process variations more efficiently without requiring exhaustive corner analysis, thus reducing the number of analysis runs needed while improving reliability.
2Ease of operation
If corner-based static timing analysis sets all parameters to worst case in one corner and best case in another, then analysis simplicity is improved, but design accuracy deteriorates due to overly conservative or optimistic results
Solution Approach 1:
The patent implements a feedback mechanism where statistical timing analysis results are aggregated across multiple simulated process variations to compute actual yield metrics. This feedback loop allows the methodology to identify whether corner-based assumptions are overly conservative or optimistic and adjust the statistical parameters accordingly, thereby improving measurement precision while maintaining analytical tractability through statistical aggregation rather than exhaustive corner enumeration.
3Measurement precision
If the number of corner based static timing analysis runs is increased to perform exhaustive analysis, then timing analysis accuracy is improved, but run-time increases excessively
Solution Approach 1:
The patent performs preliminary action by pre-generating statistical process parameters with established correlation structures before the timing analysis. By preparing the statistical model in advance with realistic process variation characteristics, the method enables accurate timing analysis with far fewer simulation runs compared to exhaustive corner-based approaches, significantly reducing analysis run-time while maintaining or improving precision through better statistical representation.
Data Source
AI summary
In one embodiment of the invention, a method of analysis of a circuit design is disclosed to generate a statistical timing model. The method includes receiving a timing graph of a circuit including arcs with a statistical function of delay, slew, or arrival time; determining primary input ports and output ports of the circuit; identifying timing pins between the input ports and the output ports of the circuit; and evaluating the timing pins from input ports to output ports to reduce the timing graph to ease analysis of the reduced timing graph with a processor.