Static Timing Model Correction for Unbalanced Edge-Rates
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Solution Overview
Problem
Existing static-timing models for digital integrated circuits are inaccurate when dealing with circuit elements having unbalanced edge-rates, leading to timing delay discrepancies between statistical and fixed-corner models, which can result in incorrect chip design and performance.
Innovation Solution
The method involves evaluating timing delays using both statistical and fixed-corner models for circuit elements with unbalanced edge-rates, calculating a timing delay error, and correcting the computed timing delays in static-timing models to improve accuracy, utilizing a data storage device with machine-readable instructions to adapt processors for this calculation and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional static-timing models are used for circuit elements with unbalanced edge-rates, then computational simplicity is maintained, but timing delay accuracy deteriorates
Solution Approach 1:
The patent introduces an intermediary correction mechanism that bridges the gap between simple static-timing models and accurate dynamic behavior. A correction factor is computed based on edge-rate conditions and applied to adjust timing delays, allowing the use of simple models while achieving accurate results through the intermediary correction step.
Solution Approach 2:
The patent dynamically adjusts timing delay parameters based on edge-rate conditions. When edge-rates are unbalanced, correction factors are applied to modify the timing delay values, transforming the static parameters into adaptive values that reflect actual circuit behavior under varying edge-rate conditions.
2Measurement precision
If statistical models are used to evaluate timing delays for unbalanced circuit elements, then timing delay accuracy is improved, but computational time increases
Solution Approach 1:
The patent applies partial correction rather than full statistical analysis. By computing correction factors based on edge-rate conditions and applying them to static-timing model results, the method achieves improved accuracy without performing complete statistical simulations, thus reducing computational time while maintaining necessary precision.
Solution Approach 2:
The patent performs preliminary computation of correction factors based on edge-rate conditions before final timing delay calculation. This preliminary action allows the main timing analysis to use simplified models while incorporating accuracy improvements, avoiding the need for time-consuming statistical simulations during the main design flow.
Data Source
AI summary
Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing delay error between the two models. The timing delay error may then be used to correct timing delays computed by static-timing models for similar unbalanced circuit elements within a more complex digital circuit.