Circuit Design Layout Pattern Error Identification

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional Layout Versus Schematic (LVS) tools face challenges in precisely locating short circuit violations, as they highlight the entire short circuit pattern rather than pinpointing the exact location, making it difficult to correct errors efficiently.

Innovation Solution

A method and system that involve extracting design data, assigning IDs to layout designs based on net names and connective layer names, and using these IDs to identify and display short circuit points through a Design Rule Check (DRC) tool, allowing for precise identification and correction of short circuit errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If LVS tool highlights the whole short circuit pattern, then the short circuit violation is detected, but the precise short circuit location cannot be determined

Engineering Contradiction:

Improveshort circuit location precisionVSAvoidinformation loss in error localization

Core Design Contradiction:

Measurement precisionVSLoss of information

Solution Approach 1:

The patent divides the short circuit pattern into individual short circuit points by introducing a window that moves across the layout. Each position of the window identifies a specific short circuit point, thereby segmenting the overall violation pattern into locatable discrete error locations that can be precisely identified and corrected

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a window as an intermediary element between the LVS tool and the short circuit pattern. This window serves as a mediator that scans across the layout and isolates specific short circuit points, enabling precise location identification without losing the contextual information about the overall short circuit violation

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If the whole short circuit pattern is highlighted, then short circuit violations are detected, but the operation time to correct errors increases

Engineering Contradiction:

Improveerror correction efficiencyVSAvoidtime to locate and correct short circuit errors

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by pre-defining a window structure and establishing the scanning mechanism before actual error detection. The window is prepared in advance with defined dimensions and movement parameters, enabling rapid sequential identification of short circuit points without requiring complex post-processing analysis

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements skipping by moving the window systematically across the layout in a scanning motion that rapidly jumps from one potential short circuit location to the next. This rushing through the layout with a predefined window structure enables quick identification of all short circuit points, significantly reducing the time needed to locate and correct errors compared to analyzing the entire pattern at once

Inventive Principle:

Principle #21Skipping (Rushing through)

Data Source

PatentUS11200364B2Method and associated system for circuit design

Publication Date: 2021.12.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method, includes: extracting a design data using a computer, wherein the design data includes a net name and a connective layer name of each layout design in each cell; generating a layout pattern corresponding to the design data by assigning an ID to said each layout design, wherein the ID includes a first indicator indicative of the net name and a second indicator indicative of the connective layer name; and checking the layout pattern to locate an error of the layout pattern.