Multi-pass Fill and Cheese Structure Design for CMP Flatness
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Solution Overview
Problem
Existing methods for generating fill and cheese structures in integrated circuits and printed circuit boards lack precision, as the location, size, and shape of these structures are unknown to circuit designers, leading to inaccurate assumptions about their effects on circuit function, especially as circuit size decreases and in analog circuits.
Innovation Solution
A multi-pass method allows circuit designers to designate the placement of fill and cheese structures during the design process, using forbidden areas to ensure spacing and connectivity, enabling precise control over these structures before dataprep, and allowing for iterative generation across multiple levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fill structures are inserted to increase layout pattern density, then CMP surface flatness is improved, but circuit designer's knowledge of structure location and effect is reduced
Solution Approach 1:
The patent applies preliminary action by allowing circuit designers to specify fill structure parameters (density, size, shape) during the design phase before manufacturing. This enables designers to have knowledge of and control over fill structure characteristics while still achieving the required CMP surface flatness through pre-planned density control.
2Manufacturing precision
If cheese structures are removed to decrease layout pattern density, then CMP surface flatness is improved, but precision of circuit function prediction is reduced
Solution Approach 1:
The patent enables preliminary specification of cheese structure parameters during design, allowing designers to predict circuit function accurately while controlling layout density to achieve proper CMP surface flatness.
3Ease of manufacture
If fill structures are generated during dataprep with assumed uniform distribution, then manufacturing process is simplified, but accuracy of analog circuit design is reduced
Solution Approach 1:
The patent applies local quality by allowing different fill structure parameters (density, size, shape, distribution) to be specified in different regions of the layout. This enables high-precision control for sensitive analog circuits while maintaining manufacturing feasibility through localized rather than uniformly complex specifications.
Data Source
AI summary
A multi-pass method for designing at least a portion of a circuit layout on a substrate is provided which includes receiving or generating a first level frame including an electrical component; generating a fill pattern on the first level frame outside of a forbidden area of said first level frame; generating a next level frame, the next level frame including the first level frame and a next level fill area outside of the first level frame; and adding a conductor to the next level frame. The conductor is connected to the electrical component, a first portion of the conductor is in the first level frame and a second portion of the conductor is in the next level fill area. The method includes generating a next fill pattern on the next level fill area outside of a forbidden area of said next level fill area, modifying the first level forbidden area to extend at least over the electrical component and the first portion of the conductor, and removing any of the plurality of structures in the fill pattern that are within the modified first level forbidden area.