Semiconductor Pin Routing Automation via Net List Generation
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Solution Overview
Problem
Existing semiconductor device testing methods face challenges in efficiently generating routings between pins without a library, particularly in the early stages of design, where pin locations and geometrical information are limited, leading to difficulties in optimizing routing efficiency and increasing the number of testable device elements.
Innovation Solution
A method that involves selecting candidate pins based on density, shape, size, and interval adjustments, generating a net list, and using a library-based disposition and wiring tool to automatically generate routings between pins, enabling efficient electrical connections without relying on a pre-existing cell library.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If a library-based routing mode is used, then routing automation is achieved, but it cannot be applied at early design stages before cell library generation
Solution Approach 1:
The patent performs preliminary actions by generating pin location information and geometric data before cell library creation. The system prepares routing-capable data structures and pin configurations in advance, enabling automated routing tools to function at early design stages when traditional libraries are not yet available.
Solution Approach 2:
The patent introduces an intermediary layer that translates early-stage pin location data into a format compatible with library-based routing tools. This intermediary data structure acts as a bridge, allowing automated routing algorithms to operate on preliminary design information without requiring a complete cell library.
2Quantity of substance
If pin density is increased to test more device elements, then testing coverage improves, but routing complexity and difficulty increase
Solution Approach 1:
The patent segments the routing problem by individually processing each pin's location information and geometric characteristics. By breaking down the complex routing task into discrete pin-level operations, the system can handle high pin densities without being overwhelmed by overall routing complexity.
Solution Approach 2:
The patent changes key parameters including pin location coordinates, geometric shapes, and interval measurements to optimize routing configurations. By adjusting these parameters based on density requirements, the system increases testable device elements while managing routing complexity through parameter optimization.
3Adaptability or versatility
If manual routing methods are used without a library, then early design stage flexibility is maintained, but routing efficiency and productivity decrease
Solution Approach 1:
The patent enables the system to serve itself by automatically generating pin location information and routing configurations without requiring external cell library inputs. The automated tool set processes preliminary design data independently, maintaining early-stage flexibility while achieving routing efficiency through self-contained automated operations.
4Productivity
If pin locations and geometries are optimized for routing, then routing efficiency improves, but the preprocessing complexity increases
Solution Approach 1:
The patent performs preliminary optimization of pin locations and geometric shapes before the actual routing process. By pre-calculating optimal pin configurations and storing location information in advance, the system reduces routing complexity while maintaining high routing efficiency through pre-optimized parameters.
Data Source
AI summary
Generating a routing between pins of a semiconductor device may include selecting one or more of candidate pins of the semiconductor device, generating a net list associated with the selected pins generating an interface script to execute the net list in a library-based disposition and wiring tool that is driven in a computer system, and executing the interface script through the library-based disposition. Pins may be selected from the candidate pins based on at least one of density, shapes, intervals, and sizes among the candidate pins. The net list may define a set of electrical connections between the selected pins.