Automated Double Patterning Loop Violation Detection in IC Layouts
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Solution Overview
Problem
Current photolithographic processes face challenges in increasing feature density due to pitch constraints, leading to difficulties in identifying and correcting double patterning (DP) loop violations in IC design layouts, which can result in printing errors.
Innovation Solution
A method is developed to automatically and accurately identify DP loop violations by using graph tracing techniques and breadth-first search to assign colors to nodes, generating markers for each identified loop to indicate DP loop violations, and displaying these markers in the design layout to facilitate corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning lithography is used to increase feature density, then manufacturing precision is improved, but the complexity of identifying and correcting DP loop violations increases
Solution Approach 1:
The patent replaces manual graph tracing and DP loop violation identification with an automated computer-implemented method. The system automatically performs graph tracing, color assignment, and violation detection through software execution, eliminating the need for manual analysis and reducing complexity in the identification process.
Solution Approach 2:
The system enables self-service by automatically generating markers that directly indicate DP loop violations in the design layout. The automated method performs the entire identification and marking process without requiring external intervention, allowing designers to quickly locate and correct violations.
2Productivity
If manual graph tracing methods are used to identify DP loop violations, then false identifications may occur, but automation increases productivity
Solution Approach 1:
The patent replaces manual graph tracing with an automated computer-implemented method that systematically performs breadth-first search, color assignment, and violation detection. This automation eliminates human error and ensures consistent, accurate identification of DP loop violations while significantly increasing productivity.
Solution Approach 2:
The system provides feedback by generating visual markers that directly indicate the location and nature of DP loop violations in the design layout. This feedback mechanism allows designers to verify the accuracy of identified violations and make necessary corrections efficiently.
Data Source
AI summary
Some embodiments of the invention provide a method for automatically, accurately, and efficiently identifying double patterning (DP) loop violations in an IC design layout. The method of some embodiments identifies DP loop violations in a manner that eliminates false identification of DP loop violations without missing DP loop violations that should be identified. The method of some embodiments also generates a marker for each identified DP loop violation to indicate that a set of shapes associated with the marker forms the DP loop and displays the marker in the design layout.