Automated EDA Tool for Stacked Die Interconnect Verification
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Solution Overview
Problem
Debugging stacked dies in 2.5D and 3D IC packaging is tedious, time-consuming, and error-prone, often requiring respinning due to the complexity of inter-die connectivity and microbump mapping errors.
Innovation Solution
An automated electronic design automation (EDA) tool is employed to parse, compare, and correct gate-level descriptions and microbump mapping files across multiple dies, ensuring accurate interconnections by generating verified output data sets and correcting discrepancies automatically or manually.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If automated EDA tools are used to verify inter-die connectivity, then debugging time and error rate are reduced, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary verification system that acts as a mediator between the complex inter-die connectivity structures and the debugging process. This verification toolset serves as an intermediate layer that automatically checks connectivity without requiring manual debugging of the complex stacked die configurations, thereby reducing debugging time while managing system complexity through automation.
Solution Approach 2:
The patent replaces manual mechanical debugging processes with automated electronic verification systems. Instead of physically inspecting and debugging inter-die connections manually, the system uses automated EDA tools to electronically verify connectivity, substituting the mechanical/manual debugging approach with an automated computational system that reduces time loss despite increased system complexity.
2Productivity
If manual debugging of stacked dies is performed, then device complexity remains low, but productivity decreases and error rate increases
Solution Approach 1:
The patent applies preliminary action by performing verification of inter-die connectivity before the actual packaging process is completed. The automated EDA tools verify connections in advance, identifying potential errors before they propagate through the manufacturing process. This preliminary verification increases productivity by preventing rework while introducing verification system complexity.
Solution Approach 2:
The patent implements feedback mechanisms where the verification system continuously monitors and provides information about inter-die connectivity status. This feedback loop allows for real-time detection and correction of errors, improving packaging process efficiency. The feedback system increases verification complexity but enables automated quality control that outweighs the added complexity.
3Manufacturing precision
If comprehensive verification of microbump mapping is performed, then manufacturing precision improves, but loss of time increases due to verification complexity
Solution Approach 1:
The patent applies partial action by focusing verification efforts on critical inter-die connections rather than performing exhaustive verification of all possible connections. The automated EDA tools prioritize verification of high-risk or high-impact connections, achieving sufficient manufacturing precision without the time cost of complete verification of every connection in the stacked die structure.
Solution Approach 2:
The patent changes verification parameters by adjusting the depth and scope of verification based on connection criticality. The system dynamically modifies verification parameters such as sampling rate, check depth, and validation strictness depending on the specific inter-die connection being verified. This parameter adaptation maintains manufacturing precision for critical connections while reducing verification time for less critical connections.
Data Source
AI summary
A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.