Multithreaded Static Timing Analysis for Chip Design
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Solution Overview
Problem
Conventional static timing analysis tools for digital circuits are inefficient due to their complexity, leading to lengthy analysis times as they use path-oriented approaches that exponentially increase with the number of nodes in the circuit, making them impractical for high-performance integrated circuits.
Innovation Solution
A multithreaded algorithm that traverses the chip circuit to identify nodes, assigns levels, and processes them in parallel using an optimum number of threads, dynamically adjusting thread counts based on node grouping sizes to facilitate faster analysis by reducing processing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional path-oriented STA approach is used, then timing analysis can be performed with simplified delay models, but analysis time increases exponentially with the number of nodes
Solution Approach 1:
The patent segments the circuit nodes into different levels based on their timing relationships, creating a hierarchical structure. This segmentation allows the algorithm to process nodes level-by-level rather than traversing all possible paths, reducing the exponential complexity to polynomial time while maintaining timing analysis accuracy through systematic level-based processing.
Solution Approach 2:
The patent dynamically adjusts the number of processing threads based on the circuit characteristics and available computational resources. This dynamic threading strategy optimizes parallel processing efficiency, allowing the algorithm to scale with problem size and hardware capabilities, thereby reducing analysis time without sacrificing precision.
2Productivity
If the number of processing threads is increased, then parallel processing speed increases, but system complexity and resource management overhead increase
Solution Approach 1:
The patent implements dynamic thread management where the number of active threads is adjusted based on the current processing stage and circuit characteristics. This dynamic approach allows the system to optimize parallel processing speed while avoiding the overhead of managing excessive threads, adapting the complexity to the actual computational needs at each processing stage.
Solution Approach 2:
The patent changes the threading parameter adaptively based on problem size and hardware resources. By adjusting this parameter dynamically rather than using a fixed thread count, the system achieves optimal processing speed across different circuit complexities while keeping management complexity proportional to actual needs rather than maximum potential.
Data Source
AI summary
A method and apparatus for executing multithreaded algorithm to provide static timing analysis of a chip design includes analyzing a chip design to identify various components and nodes associated with the components. A node tree is built with a plurality of nodes. The node tree identifies groups of nodes that are available in different levels. A size of node grouping for a current level is determined by looking up the node tree. Testing data for parallel processing of different size of node groupings using varied thread counts is compiled. An optimum thread count for the current level based on the size of node grouping in the node tree is identified from compiled testing data. Dynamic parallel processing of nodes in the current level is performed using the number of threads identified by the optimum thread count. An acceptable design of the chip is determined by the dynamic parallel processing.