Automatic Hierarchy-Independent Circuit Partitioning for VLSI Simulation
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Solution Overview
Problem
Conventional circuit simulation techniques, such as SPICE and Fast-SPICE, face challenges with large VLSI circuits having non-ideal power supplies, leading to slow and inaccurate simulations due to large partition sizes and the need for manual engineer input, as well as synchronous evaluation requirements that hinder parallel processing and memory efficiency.
Innovation Solution
An automatic hierarchy-independent partitioning method that identifies cut points and synchronizes blocks using topological analysis and sparse matrix solvers, allowing for asynchronous simulation of blocks connected at channels or rails, thereby reducing fill-ins and optimizing memory and time usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If partitioning is used to decouple weakly-connected circuit components, then simulation time and memory requirements are reduced, but accuracy is lost for circuits with non-ideal power supplies
Solution Approach 1:
The circuit is partitioned into multiple blocks by identifying cut points at power net connections. Each block can be simulated independently or asynchronously, reducing overall simulation complexity while maintaining accuracy through proper handling of non-ideal power supplies within each block
Solution Approach 2:
The method changes the parameter representation by treating driver blocks as ideal voltage sources and using sparse matrix solvers to minimize fill-ins. This allows accurate simulation of non-ideal power supplies while maintaining the benefits of partitioning
2Measurement precision
If manual engineer input is used to designate cut points, then partitioning accuracy is improved, but ease of operation and automation are reduced
Solution Approach 1:
The system performs self-service by automatically identifying cut points through topological analysis and sparse matrix solver algorithms. The method independently determines optimal partition locations without requiring manual engineer input, achieving both high automation and accurate partitioning
Solution Approach 2:
The manual process of designating cut points is replaced with an automated computational system using topological analysis and sparse matrix solvers. This substitution maintains partitioning accuracy while eliminating the need for manual intervention
3Reliability
If synchronous evaluation of all blocks is required, then reliability of simulation results is improved, but productivity and ease of operation are reduced
Solution Approach 1:
The simulation method transitions from static synchronous evaluation to dynamic asynchronous evaluation. Blocks can be evaluated at different times based on their readiness, enabling parallel processing while maintaining result reliability through proper synchronization mechanisms when needed
4Quantity of substance
If partitioning is applied to circuits with non-ideal power supplies, then memory requirements are reduced, but device complexity and difficulty of detecting and measuring increase
Solution Approach 1:
Complex manual partitioning analysis is replaced with automated topological analysis and sparse matrix solver algorithms. This substitution reduces the perceived complexity by providing a systematic, algorithm-driven approach to partitioning circuits with non-ideal power supplies
Solution Approach 2:
The system automatically handles the complexity of partitioning non-ideal power supply circuits through self-service algorithms. The method independently analyzes circuit topology and determines optimal cut points without requiring external intervention, reducing both memory usage and operational complexity
Data Source
AI summary
A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.