Automated Logical Clock Connection in HDL Design
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Solution Overview
Problem
Current integrated circuit design methodologies require manual entry of complex non-functional-intent structures, such as pervasive logic and clock control structures, which leads to increased design complexity, human error, and degraded simulation performance.
Innovation Solution
Implementing a design methodology that supports multiple levels of abstraction in integrated circuit design models, allowing for the automatic addition of logical clock connections and the use of simplified HDL syntax, which reduces the need for manual entry of non-functional-intent structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual entry of non-functional-intent structures (pervasive logic, clock control structures) is required in HDL files, then complete design specification is achieved, but design complexity and human error increase significantly
Solution Approach 1:
The patent extracts non-functional-intent structures (pervasive logic, clock control structures) from manual HDL entry and handles them automatically through tool-based processing. This separates the functional design intent from the implementation details, allowing designers to focus only on functional logic while the tool automatically generates and manages support structures.
Solution Approach 2:
The design system performs self-service by automatically generating pervasive logic and clock control structures without requiring manual intervention. The toolset inspects the functional design, infers required support structures, and generates the complete HDL code including non-functional-intent portions, making the design process self-sufficient.
2Reliability
If all non-functional-intent structures are explicitly expressed in HDL files, then complete design model is created, but simulation performance degrades
Solution Approach 1:
The patent segments the design model into functional-intent portions (explicitly modeled for simulation) and non-functional-intent portions (handled automatically). This segmentation allows the simulation engine to focus only on functional logic while the toolset manages support structures separately, improving simulation performance without sacrificing design completeness.
Solution Approach 2:
The patent introduces an intermediary processing layer between design entry and simulation. This intermediary toolset automatically generates the complete design model from functional specifications, acting as a mediator that translates high-level functional intent into complete implementation models without requiring designers to manually create all structures.
3Adaptability or versatility
If manual entry of pervasive logic and clock control structures is required, then design flexibility is maintained, but coding effort and human error increase
Solution Approach 1:
The system performs self-service by automatically generating pervasive logic and clock control structures based on functional design specifications. This eliminates manual coding of support structures while maintaining design flexibility, as the toolset adapts to different design requirements automatically.
Solution Approach 2:
The patent applies preliminary action by pre-generating non-functional-intent structures based on functional design intent before simulation or implementation. This preliminary generation of support structures eliminates the need for manual coding later, reducing coding effort and errors while preserving design adaptability.
4Ease of operation
If simplified HDL syntax is used that omits logical clock connections, then coding effort is reduced, but automatic processing is required to add connections
Solution Approach 1:
The patent extracts the complexity of logical clock connection specification from the HDL syntax, allowing designers to use simplified syntax without explicitly detailing clock connections. The toolset then automatically processes this simplified code and adds the necessary clock connections, separating design intent from implementation details.
Solution Approach 2:
The patent introduces an intermediary processing step that translates simplified HDL syntax into complete code with explicit clock connections. This intermediary toolset acts as a mediator between the designer's simplified input and the simulation engine's requirements, automatically inferring and adding necessary clock connections without increasing coding effort.
Data Source
AI summary
A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.