Automatic Clock Routing in ASICs Using Standardized Grid
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Solution Overview
Problem
Conventional integrated circuit (IC) design faces challenges in efficiently and accurately routing clock signals due to irregularly shaped partitions, leading to complex manual programming, potential for sub-optimal routes, and increased labor costs from frequent design changes and human error.
Innovation Solution
A standardized grid of clock buffers is used to automatically route clocks throughout ASICs, with clock sources and sinks mapped to grid points, allowing for grid routing that bypasses blockages and optimizes power consumption by merging signal paths, reducing clock skew and congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual programming of clock routes is used for each partition configuration, then routing accuracy can be maintained, but time consumption and labor effort increase significantly
Solution Approach 1:
The patent uses a standardized template-based approach where pre-defined clock routing templates are copied and applied to different partition configurations. Instead of manually programming each route from scratch, the system selects and adapts pre-validated routing patterns, significantly reducing time consumption while maintaining routing accuracy through template reuse.
Solution Approach 2:
The system automatically adjusts routing parameters such as hop count, buffer placement, and route geometry based on detected partition characteristics. By changing parameters like the number of routing steps or buffer positions according to partition size and shape, the system adapts standardized templates to specific configurations without manual reprogramming.
2Productivity
If standardized clock routing templates are used, then routing time is reduced, but routing optimization for irregular partitions may be compromised
Solution Approach 1:
The patent applies different routing template characteristics to different regions of the chip based on local partition requirements. For example, irregular partitions receive customized buffer placements or route geometries specific to their shape, while regular partitions use standard templates. This local adaptation ensures optimization is maintained where needed without sacrificing overall routing speed.
Solution Approach 2:
The routing system dynamically selects and modifies templates based on real-time analysis of partition configurations. When a partition deviates from standard geometry, the system automatically adjusts the template parameters or selects alternative templates, ensuring optimized routing adapts to local requirements while maintaining high productivity through automated template-based processing.
3Ease of operation
If manual route specification is performed for each step, then routing control is precise, but error potential and labor costs increase
Solution Approach 1:
The system performs self-configuration by automatically detecting partition geometries, selecting appropriate routing templates, and generating complete clock routes without manual intervention. The routing tool autonomously handles tasks such as buffer placement, route geometry generation, and parameter adjustment, eliminating the need for manual step-by-step specification while maintaining precise routing control through automated validation.
Solution Approach 2:
The patent incorporates validation feedback mechanisms that automatically verify routing correctness against partition specifications. The system checks for issues such as incorrect hop counts, improper buffer placements, or route geometry errors, and automatically corrects or re-selects templates based on feedback from validation algorithms, reducing human error without requiring manual verification.
4Reliability
If clock routing macros are embedded in partitions, then signal propagation is enabled, but reconfiguration difficulty increases when design changes occur
Solution Approach 1:
The patent segments the clock routing functionality into independent, modular components such as separate buffer macros and routing segments that can be individually replaced. When design changes occur, only the affected segments need to be reconfigured rather than replacing entire embedded macros, making the system more flexible and easier to reconfigure while maintaining reliable signal propagation through proper segmentation of routing functions.
Data Source
AI summary
Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.