Automated Clock Signal Provisioning in Integrated Circuits
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Solution Overview
Problem
Manual instantiation and routing of clock signals in integrated circuits is time-consuming and inefficient, especially for designs with relaxed timing constraints, as it requires manual effort and does not allow for automation of clock signal provisioning between multiple cores within the same clock domain.
Innovation Solution
A method for automating clock signal provisioning within integrated circuits by gathering information about the circuit and its environment, instantiating compatible cores, and routing interconnects to supply compliant clock signals, using hardware design synthesis tools to derive and route clock signals from peripheral components like fixed-frequency oscillators to cores within the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual instantiation and routing of clock signals is performed, then clock signal timing constraints can be met, but design time and manual effort increase significantly
Solution Approach 1:
The system enables automatic clock signal provisioning where the design tool automatically instantiates clock modules and routes clock signals based on core requirements, eliminating the need for manual designer intervention while ensuring timing constraints are met
Solution Approach 2:
The system performs preliminary analysis of core clock requirements and pre-configures appropriate clock modules and routing paths before final design compilation, reducing iterative manual adjustments and speeding up the overall design process
2Ease of operation
If manual clock signal provisioning is performed, then precise control over clock routing is achieved, but automation level remains low
Solution Approach 1:
The design tool automatically analyzes core clock requirements, selects appropriate clock modules, and generates routing configurations without manual intervention, achieving high automation while maintaining design integrity through systematic algorithms
Solution Approach 2:
The system continuously monitors clock signal requirements from multiple cores and adjusts clock module instantiation and routing configurations iteratively, providing automatic feedback-based optimization that replaces manual trial-and-error processes
3Productivity
If clock modules are shared between multiple cores, then resource utilization improves, but clock signal skew and loading become more difficult to manage
Solution Approach 1:
The system enables single clock modules to serve multiple cores by automatically analyzing and satisfying the clock requirements of each core, achieving resource sharing while managing signal integrity through systematic routing and loading calculations
Solution Approach 2:
The system automatically adjusts clock signal parameters such as frequency division ratios and buffering configurations when routing to multiple cores, maintaining signal quality and minimizing skew through parameter optimization rather than manual management
Data Source
AI summary
A method is provided to incorporate information currently known about an integrated circuit's design, including peripheral components that share the same printed circuit board (PCB) with the integrated circuit, to automate a clock signal instantiation and routing solution to realize a comprehensive design. The information derived from a hardware design synthesis tool includes the existence of PCB resources, such as fixed-frequency oscillators, that may co-exist with a particular integrated circuit, such as a programmable logic device (PLD). Other derived information includes details concerning clock modules and cores that may exist within the PLD in accordance with the PLD's design specification. Once the information that describes the PLD and its environment is known, the information is utilized to automatically instantiate resource interconnect cores and automatically generate connections between the fixed-frequency oscillators, resource interconnect cores, and PLD implemented cores that are contained within the design.