Circuit Layout Congestion Prevention via Virtual Blockages
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Solution Overview
Problem
High-density electronic devices in circuit layouts lead to routing congestion, making it impossible for the circuit to pass design rule checks and function properly, as the number of devices in a given area becomes too large, causing infeasible routing between them.
Innovation Solution
A congestion preventing apparatus and method that performs routing congestion analysis, disposes virtual blockages at the edges of the circuit layout to create reserved spaces, and redistributes electronic devices according to specific rules, reducing congested regions by redistributing devices within these reserved spaces after removing the blockages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a large number of electronic devices are placed in a small chip area to meet product requirements, then the chip area utilization is improved, but routing congestion occurs and design rule checks fail
Solution Approach 1:
The patent performs routing congestion analysis before final placement and identifies congested regions. Virtual blockages are disposed in advance in these congested areas to guide the placement process, preventing excessive device density that would cause routing failures. This preliminary analysis and preventive disposition resolves the contradiction by anticipating and avoiding routing congestion while maintaining high chip area utilization.
2Reliability
If virtual blockages are disposed in congested regions to prevent congestion, then routing feasibility is improved, but the placement process becomes more complex
Solution Approach 1:
The patent introduces virtual blockages as intermediary elements that temporarily occupy congested regions during the placement process. These virtual blockages act as mediators that guide device placement away from congested areas without permanently restricting the design. After placement is complete, the virtual blockages are removed, having served their purpose of preventing routing congestion while maintaining placement flexibility.
3Reliability
If electronic devices are redistributed in congested regions, then routing congestion is reduced, but the original device relationships may be disrupted
Solution Approach 1:
The patent applies different placement strategies to different regions of the chip. In non-congested regions, devices are placed according to their optimal design positions. In congested regions, virtual blockages are disposed to guide redistribution. This local differentiation allows the patent to reduce routing congestion in specific areas while preserving device relationships and placements in non-congested areas, thus maintaining overall device relationship stability.
Data Source
AI summary
A congestive placement preventing apparatus applied to a circuit layout including electrical devices is provided. The congestive placement preventing apparatus includes an analyzing module, a reserving module and a placing module. The analyzing module performs a routing congestion analysis on the circuit layout to generate an analysis result of the circuit layout. The reserving module correspondingly disposes a plurality of blockages in the circuit layout according to the analysis result, so that a first space with the blockages and a second space are formed in the circuit layout. After the placing module places the electrical devices in the second space, the placing module removes the blockages from the first space, and redistributes the electrical devices in the first space and the second space according to a redistribution rule.