Automated Error Mitigation Logic for Electronic Circuit Design
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Solution Overview
Problem
Circuit design faces challenges in balancing robust error mitigation with the cost of increased chip area, particularly in addressing random errors caused by ionizing radiation, and existing methods lack efficient automation in selecting and generating fault-tolerant logic.
Innovation Solution
The method involves automatically selecting and generating error mitigation logic for electronic system designs using a library of techniques such as TMR, DMR, scrubbing, and parity checking, based on user-specified data, and translating high-level specifications into intermediate programming languages to implement fault-tolerant circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If robust error mitigation circuitry is implemented, then reliability is improved, but chip area increases
Solution Approach 1:
The patent applies local quality by enabling selective error mitigation techniques at different locations within the circuit design. Different components can have different error mitigation strategies applied based on their criticality and risk exposure, allowing robust protection where needed while minimizing area consumption in less critical sections.
Solution Approach 2:
The system changes the parameter of error mitigation intensity by allowing users to specify desired levels of fault tolerance. The automated tool then adjusts the type and extent of error mitigation circuitry accordingly, transitioning between different robustness levels to balance reliability improvements with area constraints.
2Productivity
If automated error mitigation selection is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The automated tool performs self-service by automatically selecting and generating error mitigation strategies without requiring manual intervention in the complex decision-making process. The system autonomously analyzes the circuit design, selects appropriate error mitigation techniques, and generates the final circuit specification, significantly improving productivity while the complexity is encapsulated within the automated tool itself.
Solution Approach 2:
The patent introduces an intermediary automated tool that mediates between the high-level circuit design specification and the detailed error mitigation implementation. This intermediary layer automatically handles the complex translation and selection processes, improving productivity by abstracting away the complexity from the design process.
3Adaptability or versatility
If multiple error mitigation techniques are available, then adaptability is improved, but device complexity increases
Solution Approach 1:
The automated tool embodies universality by providing a single multi-functional system that can handle multiple error mitigation techniques (TMR, DMR, scrubbing, parity checking) through a unified interface. The tool universally processes different error mitigation strategies using the same automated framework, improving adaptability while managing complexity through standardized processing.
Solution Approach 2:
The patent segments the error mitigation techniques into distinct selectable options within the automated system. Each technique (TMR, DMR, scrubbing, parity checking) is separated as an independent technique that can be individually selected and applied to different components, allowing adaptability while the segmentation itself helps manage the complexity of the selection process.
Data Source
AI summary
Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques in response to user-specified data associated with the first specification of the design. A second specification of the design is automatically generated from the first specification. The second specification includes error mitigation logic corresponding to each selected error mitigation technique for each of the one or more components. The second specification of the design is stored for subsequent processing.